------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 2.2 -- \ \ Application : 7 Series FPGAs Transceivers Wizard -- / / Filename : gtwizard_v2_2.vhd -- /___/ /\ -- \ \ / \ -- \___\/\___\ -- -- -- Module gtwizard_v2_2 (a GT Wrapper) -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard -- -- -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.VCOMPONENTS.ALL; --***************************** Entity Declaration **************************** entity gtwizard_v2_2 is generic ( QPLL_FBDIV_TOP : integer := 16; -- Simulation attributes EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation WRAPPER_SIM_GTRESET_SPEEDUP : string := "false" -- Set to "true" to speed up sim reset ); port ( --_________________________________________________________________________ --_________________________________________________________________________ --GT0 (X0Y16) --____________________________CHANNEL PORTS________________________________ ------------------------- Channel - Ref Clock Ports ------------------------ GT0_GTREFCLK0_IN : in std_logic; -------------------------------- Channel PLL ------------------------------- GT0_CPLLFBCLKLOST_OUT : out std_logic; GT0_CPLLLOCK_OUT : out std_logic; GT0_CPLLLOCKDETCLK_IN : in std_logic; GT0_CPLLREFCLKLOST_OUT : out std_logic; GT0_CPLLRESET_IN : in std_logic; ------------------------------- Eye Scan Ports ----------------------------- GT0_EYESCANDATAERROR_OUT : out std_logic; ------------------------------- Receive Ports ------------------------------ GT0_RXUSERRDY_IN : in std_logic; --------------- Receive Ports - Comma Detection and Alignment -------------- GT0_RXSLIDE_IN : in std_logic; ------------------- Receive Ports - RX Data Path interface ----------------- GT0_GTRXRESET_IN : in std_logic; GT0_RXDATA_OUT : out std_logic_vector(19 downto 0); GT0_RXOUTCLK_OUT : out std_logic; GT0_RXUSRCLK_IN : in std_logic; GT0_RXUSRCLK2_IN : in std_logic; ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ GT0_GTHRXN_IN : in std_logic; GT0_GTHRXP_IN : in std_logic; GT0_RXCDRLOCK_OUT : out std_logic; GT0_RXELECIDLE_OUT : out std_logic; ------------------------ Receive Ports - RX PLL Ports ---------------------- GT0_RXRESETDONE_OUT : out std_logic; ------------------------------- Transmit Ports ----------------------------- GT0_TXUSERRDY_IN : in std_logic; ------------------ Transmit Ports - TX Data Path interface ----------------- GT0_GTTXRESET_IN : in std_logic; GT0_TXDATA_IN : in std_logic_vector(19 downto 0); GT0_TXOUTCLK_OUT : out std_logic; GT0_TXOUTCLKFABRIC_OUT : out std_logic; GT0_TXOUTCLKPCS_OUT : out std_logic; GT0_TXUSRCLK_IN : in std_logic; GT0_TXUSRCLK2_IN : in std_logic; ---------------- Transmit Ports - TX Driver and OOB signaling -------------- GT0_GTHTXN_OUT : out std_logic; GT0_GTHTXP_OUT : out std_logic; ----------------------- Transmit Ports - TX PLL Ports ---------------------- GT0_TXRESETDONE_OUT : out std_logic; --GT1 (X0Y27) --____________________________CHANNEL PORTS________________________________ ------------------------- Channel - Ref Clock Ports ------------------------ GT1_GTREFCLK0_IN : in std_logic; -------------------------------- Channel PLL ------------------------------- GT1_CPLLFBCLKLOST_OUT : out std_logic; GT1_CPLLLOCK_OUT : out std_logic; GT1_CPLLLOCKDETCLK_IN : in std_logic; GT1_CPLLREFCLKLOST_OUT : out std_logic; GT1_CPLLRESET_IN : in std_logic; ------------------------------- Eye Scan Ports ----------------------------- GT1_EYESCANDATAERROR_OUT : out std_logic; ------------------------------- Receive Ports ------------------------------ GT1_RXUSERRDY_IN : in std_logic; --------------- Receive Ports - Comma Detection and Alignment -------------- GT1_RXSLIDE_IN : in std_logic; ------------------- Receive Ports - RX Data Path interface ----------------- GT1_GTRXRESET_IN : in std_logic; GT1_RXDATA_OUT : out std_logic_vector(19 downto 0); GT1_RXOUTCLK_OUT : out std_logic; GT1_RXUSRCLK_IN : in std_logic; GT1_RXUSRCLK2_IN : in std_logic; ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ GT1_GTHRXN_IN : in std_logic; GT1_GTHRXP_IN : in std_logic; GT1_RXCDRLOCK_OUT : out std_logic; GT1_RXELECIDLE_OUT : out std_logic; ------------------------ Receive Ports - RX PLL Ports ---------------------- GT1_RXRESETDONE_OUT : out std_logic; ------------------------------- Transmit Ports ----------------------------- GT1_TXUSERRDY_IN : in std_logic; ------------------ Transmit Ports - TX Data Path interface ----------------- GT1_GTTXRESET_IN : in std_logic; GT1_TXDATA_IN : in std_logic_vector(19 downto 0); GT1_TXOUTCLK_OUT : out std_logic; GT1_TXOUTCLKFABRIC_OUT : out std_logic; GT1_TXOUTCLKPCS_OUT : out std_logic; GT1_TXUSRCLK_IN : in std_logic; GT1_TXUSRCLK2_IN : in std_logic; ---------------- Transmit Ports - TX Driver and OOB signaling -------------- GT1_GTHTXN_OUT : out std_logic; GT1_GTHTXP_OUT : out std_logic; ----------------------- Transmit Ports - TX PLL Ports ---------------------- GT1_TXRESETDONE_OUT : out std_logic; --____________________________COMMON PORTS________________________________ ---------------------- Common Block - Ref Clock Ports --------------------- GT0_GTREFCLK0_COMMON_IN : in std_logic; ------------------------- Common Block - QPLL Ports ------------------------ GT0_QPLLLOCK_OUT : out std_logic; GT0_QPLLLOCKDETCLK_IN : in std_logic; GT0_QPLLREFCLKLOST_OUT : out std_logic; GT0_QPLLRESET_IN : in std_logic; --____________________________COMMON PORTS________________________________ ---------------------- Common Block - Ref Clock Ports --------------------- GT1_GTREFCLK0_COMMON_IN : in std_logic; ------------------------- Common Block - QPLL Ports ------------------------ GT1_QPLLLOCK_OUT : out std_logic; GT1_QPLLLOCKDETCLK_IN : in std_logic; GT1_QPLLREFCLKLOST_OUT : out std_logic; GT1_QPLLRESET_IN : in std_logic ); end gtwizard_v2_2; architecture RTL of gtwizard_v2_2 is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of RTL : architecture is "gtwizard_v2_2,gtwizard_v2_2,{protocol_file=Start_from_scratch}"; --***********************************Parameter Declarations******************** constant DLY : time := 1 ns; --***************************** Signal Declarations ***************************** -- ground and tied_to_vcc_i signals signal tied_to_ground_i : std_logic; signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); signal tied_to_vcc_i : std_logic; signal gt0_qplloutclk_i : std_logic; signal gt0_qplloutrefclk_i : std_logic; signal gt1_qplloutclk_i : std_logic; signal gt1_qplloutrefclk_i : std_logic; signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0); signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0); signal gt1_mgtrefclktx_i : std_logic_vector(1 downto 0); signal gt1_mgtrefclkrx_i : std_logic_vector(1 downto 0); signal gt0_qpllclk_i : std_logic; signal gt0_qpllrefclk_i : std_logic; signal gt1_qpllclk_i : std_logic; signal gt1_qpllrefclk_i : std_logic; --*************************** Component Declarations ************************** component gtwizard_v2_2_GT generic ( -- Simulation attributes GT_SIM_GTRESET_SPEEDUP : string := "false"; EXAMPLE_SIMULATION : integer := 0; TXSYNC_OVRD_IN : bit := '0'; TXSYNC_MULTILANE_IN : bit := '0' ); port ( ---------------------------------- Channel --------------------------------- QPLLCLK_IN : in std_logic; QPLLREFCLK_IN : in std_logic; ------------------------- Channel - Ref Clock Ports ------------------------ GTREFCLK0_IN : in std_logic; -------------------------------- Channel PLL ------------------------------- CPLLFBCLKLOST_OUT : out std_logic; CPLLLOCK_OUT : out std_logic; CPLLLOCKDETCLK_IN : in std_logic; CPLLREFCLKLOST_OUT : out std_logic; CPLLRESET_IN : in std_logic; ------------------------------- Eye Scan Ports ----------------------------- EYESCANDATAERROR_OUT : out std_logic; ------------------------------- Receive Ports ------------------------------ RXUSERRDY_IN : in std_logic; --------------- Receive Ports - Comma Detection and Alignment -------------- RXSLIDE_IN : in std_logic; ------------------- Receive Ports - RX Data Path interface ----------------- GTRXRESET_IN : in std_logic; RXDATA_OUT : out std_logic_vector(19 downto 0); RXOUTCLK_OUT : out std_logic; RXUSRCLK_IN : in std_logic; RXUSRCLK2_IN : in std_logic; ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ GTHRXN_IN : in std_logic; GTHRXP_IN : in std_logic; RXCDRLOCK_OUT : out std_logic; RXELECIDLE_OUT : out std_logic; ------------------------ Receive Ports - RX PLL Ports ---------------------- RXRESETDONE_OUT : out std_logic; ------------------------------- Transmit Ports ----------------------------- TXUSERRDY_IN : in std_logic; ------------------ Transmit Ports - TX Data Path interface ----------------- GTTXRESET_IN : in std_logic; TXDATA_IN : in std_logic_vector(19 downto 0); TXOUTCLK_OUT : out std_logic; TXOUTCLKFABRIC_OUT : out std_logic; TXOUTCLKPCS_OUT : out std_logic; TXUSRCLK_IN : in std_logic; TXUSRCLK2_IN : in std_logic; ---------------- Transmit Ports - TX Driver and OOB signaling -------------- GTHTXN_OUT : out std_logic; GTHTXP_OUT : out std_logic; ----------------------- Transmit Ports - TX PLL Ports ---------------------- TXRESETDONE_OUT : out std_logic ); end component; --*************************Logic to set Attribute QPLL_FB_DIV***************************** impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is begin if (qpllfbdiv_top = 16) then return "0000100000"; elsif (qpllfbdiv_top = 20) then return "0000110000" ; elsif (qpllfbdiv_top = 32) then return "0001100000" ; elsif (qpllfbdiv_top = 40) then return "0010000000" ; elsif (qpllfbdiv_top = 64) then return "0011100000" ; elsif (qpllfbdiv_top = 66) then return "0101000000" ; elsif (qpllfbdiv_top = 80) then return "0100100000" ; elsif (qpllfbdiv_top = 100) then return "0101110000" ; else return "0000000000" ; end if; end function; impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is begin if (qpllfbdiv_top = 16) then return '1'; elsif (qpllfbdiv_top = 20) then return '1' ; elsif (qpllfbdiv_top = 32) then return '1' ; elsif (qpllfbdiv_top = 40) then return '1' ; elsif (qpllfbdiv_top = 64) then return '1' ; elsif (qpllfbdiv_top = 66) then return '0' ; elsif (qpllfbdiv_top = 80) then return '1' ; elsif (qpllfbdiv_top = 100) then return '1' ; else return '1' ; end if; end function; constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP); constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP); --********************************* Main Body of Code************************** begin tied_to_ground_i <= '0'; tied_to_ground_vec_i(63 downto 0) <= (others => '0'); tied_to_vcc_i <= '1'; gt0_qpllclk_i <= gt0_qplloutclk_i; gt0_qpllrefclk_i <= gt0_qplloutrefclk_i; gt1_qpllclk_i <= gt1_qplloutclk_i; gt1_qpllrefclk_i <= gt1_qplloutrefclk_i; --------------------------- GT Instances ------------------------------- --_________________________________________________________________________ --_________________________________________________________________________ --GT0 (X0Y16) gt0_gtwizard_v2_2_i : gtwizard_v2_2_GT generic map ( -- Simulation attributes GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP, EXAMPLE_SIMULATION => EXAMPLE_SIMULATION, TXSYNC_OVRD_IN => ('0'), TXSYNC_MULTILANE_IN => ('0') ) port map ( ---------------------------------- Channel --------------------------------- QPLLCLK_IN => gt0_qpllclk_i, QPLLREFCLK_IN => gt0_qpllrefclk_i, ------------------------- Channel - Ref Clock Ports ------------------------ GTREFCLK0_IN => GT0_GTREFCLK0_IN, -------------------------------- Channel PLL ------------------------------- CPLLFBCLKLOST_OUT => GT0_CPLLFBCLKLOST_OUT, CPLLLOCK_OUT => GT0_CPLLLOCK_OUT, CPLLLOCKDETCLK_IN => GT0_CPLLLOCKDETCLK_IN, CPLLREFCLKLOST_OUT => GT0_CPLLREFCLKLOST_OUT, CPLLRESET_IN => GT0_CPLLRESET_IN, ------------------------------- Eye Scan Ports ----------------------------- EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT, ------------------------------- Receive Ports ------------------------------ RXUSERRDY_IN => GT0_RXUSERRDY_IN, --------------- Receive Ports - Comma Detection and Alignment -------------- RXSLIDE_IN => GT0_RXSLIDE_IN, ------------------- Receive Ports - RX Data Path interface ----------------- GTRXRESET_IN => GT0_GTRXRESET_IN, RXDATA_OUT => GT0_RXDATA_OUT, RXOUTCLK_OUT => GT0_RXOUTCLK_OUT, RXUSRCLK_IN => GT0_RXUSRCLK_IN, RXUSRCLK2_IN => GT0_RXUSRCLK2_IN, ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ GTHRXN_IN => GT0_GTHRXN_IN, GTHRXP_IN => GT0_GTHRXP_IN, RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, RXELECIDLE_OUT => GT0_RXELECIDLE_OUT, ------------------------ Receive Ports - RX PLL Ports ---------------------- RXRESETDONE_OUT => GT0_RXRESETDONE_OUT, ------------------------------- Transmit Ports ----------------------------- TXUSERRDY_IN => GT0_TXUSERRDY_IN, ------------------ Transmit Ports - TX Data Path interface ----------------- GTTXRESET_IN => GT0_GTTXRESET_IN, TXDATA_IN => GT0_TXDATA_IN, TXOUTCLK_OUT => GT0_TXOUTCLK_OUT, TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT, TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT, TXUSRCLK_IN => GT0_TXUSRCLK_IN, TXUSRCLK2_IN => GT0_TXUSRCLK2_IN, ---------------- Transmit Ports - TX Driver and OOB signaling -------------- GTHTXN_OUT => GT0_GTHTXN_OUT, GTHTXP_OUT => GT0_GTHTXP_OUT, ----------------------- Transmit Ports - TX PLL Ports ---------------------- TXRESETDONE_OUT => GT0_TXRESETDONE_OUT ); --_________________________________________________________________________ --_________________________________________________________________________ --GT1 (X0Y27) gt1_gtwizard_v2_2_i : gtwizard_v2_2_GT generic map ( -- Simulation attributes GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP, EXAMPLE_SIMULATION => EXAMPLE_SIMULATION, TXSYNC_OVRD_IN => ('0'), TXSYNC_MULTILANE_IN => ('0') ) port map ( ---------------------------------- Channel --------------------------------- QPLLCLK_IN => gt1_qpllclk_i, QPLLREFCLK_IN => gt1_qpllrefclk_i, ------------------------- Channel - Ref Clock Ports ------------------------ GTREFCLK0_IN => GT1_GTREFCLK0_IN, -------------------------------- Channel PLL ------------------------------- CPLLFBCLKLOST_OUT => GT1_CPLLFBCLKLOST_OUT, CPLLLOCK_OUT => GT1_CPLLLOCK_OUT, CPLLLOCKDETCLK_IN => GT1_CPLLLOCKDETCLK_IN, CPLLREFCLKLOST_OUT => GT1_CPLLREFCLKLOST_OUT, CPLLRESET_IN => GT1_CPLLRESET_IN, ------------------------------- Eye Scan Ports ----------------------------- EYESCANDATAERROR_OUT => GT1_EYESCANDATAERROR_OUT, ------------------------------- Receive Ports ------------------------------ RXUSERRDY_IN => GT1_RXUSERRDY_IN, --------------- Receive Ports - Comma Detection and Alignment -------------- RXSLIDE_IN => GT1_RXSLIDE_IN, ------------------- Receive Ports - RX Data Path interface ----------------- GTRXRESET_IN => GT1_GTRXRESET_IN, RXDATA_OUT => GT1_RXDATA_OUT, RXOUTCLK_OUT => GT1_RXOUTCLK_OUT, RXUSRCLK_IN => GT1_RXUSRCLK_IN, RXUSRCLK2_IN => GT1_RXUSRCLK2_IN, ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ GTHRXN_IN => GT1_GTHRXN_IN, GTHRXP_IN => GT1_GTHRXP_IN, RXCDRLOCK_OUT => GT1_RXCDRLOCK_OUT, RXELECIDLE_OUT => GT1_RXELECIDLE_OUT, ------------------------ Receive Ports - RX PLL Ports ---------------------- RXRESETDONE_OUT => GT1_RXRESETDONE_OUT, ------------------------------- Transmit Ports ----------------------------- TXUSERRDY_IN => GT1_TXUSERRDY_IN, ------------------ Transmit Ports - TX Data Path interface ----------------- GTTXRESET_IN => GT1_GTTXRESET_IN, TXDATA_IN => GT1_TXDATA_IN, TXOUTCLK_OUT => GT1_TXOUTCLK_OUT, TXOUTCLKFABRIC_OUT => GT1_TXOUTCLKFABRIC_OUT, TXOUTCLKPCS_OUT => GT1_TXOUTCLKPCS_OUT, TXUSRCLK_IN => GT1_TXUSRCLK_IN, TXUSRCLK2_IN => GT1_TXUSRCLK2_IN, ---------------- Transmit Ports - TX Driver and OOB signaling -------------- GTHTXN_OUT => GT1_GTHTXN_OUT, GTHTXP_OUT => GT1_GTHTXP_OUT, ----------------------- Transmit Ports - TX PLL Ports ---------------------- TXRESETDONE_OUT => GT1_TXRESETDONE_OUT ); --_________________________________________________________________________ --_________________________________________________________________________ --_________________________GTHE2_COMMON____________________________________ gthe2_common_0_i : GTHE2_COMMON generic map ( -- Simulation attributes SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP, SIM_QPLLREFCLK_SEL => ("001"), SIM_VERSION => ("2.0"), ------------------COMMON BLOCK Attributes--------------- BIAS_CFG => (x"0000040000001000"), COMMON_CFG => (x"00000000"), QPLL_CFG => (x"0480181"), QPLL_CLKOUT_CFG => ("0000"), QPLL_COARSE_FREQ_OVRD => ("010000"), QPLL_COARSE_FREQ_OVRD_EN => ('0'), QPLL_CP => ("0000011111"), QPLL_CP_MONITOR_EN => ('0'), QPLL_DMONITOR_SEL => ('0'), QPLL_FBDIV => (QPLL_FBDIV_IN), QPLL_FBDIV_MONITOR_EN => ('0'), QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO), QPLL_INIT_CFG => (x"000006"), QPLL_LOCK_CFG => (x"05E8"), QPLL_LPF => ("1111"), QPLL_REFCLK_DIV => (1), RSVD_ATTR0 => (x"0000"), RSVD_ATTR1 => (x"0000"), QPLL_RP_COMP => ('0'), QPLL_VTRL_RESET => ("00"), RCAL_CFG => ("00") ) port map ( ------------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- DRPADDR => tied_to_ground_vec_i(7 downto 0), DRPCLK => tied_to_ground_i, DRPDI => tied_to_ground_vec_i(15 downto 0), DRPDO => open, DRPEN => tied_to_ground_i, DRPRDY => open, DRPWE => tied_to_ground_i, ---------------------- Common Block - Ref Clock Ports --------------------- GTGREFCLK => tied_to_ground_i, GTNORTHREFCLK0 => tied_to_ground_i, GTNORTHREFCLK1 => tied_to_ground_i, GTREFCLK0 => GT0_GTREFCLK0_COMMON_IN, GTREFCLK1 => tied_to_ground_i, GTSOUTHREFCLK0 => tied_to_ground_i, GTSOUTHREFCLK1 => tied_to_ground_i, ------------------------- Common Block - QPLL Ports ------------------------ BGRCALOVRDENB => tied_to_vcc_i, PMARSVDOUT => open, QPLLDMONITOR => open, QPLLFBCLKLOST => open, QPLLLOCK => GT0_QPLLLOCK_OUT, QPLLLOCKDETCLK => GT0_QPLLLOCKDETCLK_IN, QPLLLOCKEN => tied_to_vcc_i, QPLLOUTCLK => gt0_qplloutclk_i, QPLLOUTREFCLK => gt0_qplloutrefclk_i, QPLLOUTRESET => tied_to_ground_i, QPLLPD => tied_to_ground_i, QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_OUT, QPLLREFCLKSEL => "001", QPLLRESET => GT0_QPLLRESET_IN, QPLLRSVD1 => "0000000000000000", QPLLRSVD2 => "11111", REFCLKOUTMONITOR => open, ----------------------------- Common Block Ports --------------------------- BGBYPASSB => tied_to_vcc_i, BGMONITORENB => tied_to_vcc_i, BGPDB => tied_to_vcc_i, BGRCALOVRD => "00000", PMARSVD => "00000000", RCALENB => tied_to_vcc_i ); --_________________________________________________________________________ --_________________________________________________________________________ --_________________________GTHE2_COMMON____________________________________ gthe2_common_1_i : GTHE2_COMMON generic map ( -- Simulation attributes SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP, SIM_QPLLREFCLK_SEL => ("001"), SIM_VERSION => ("2.0"), ------------------COMMON BLOCK Attributes--------------- BIAS_CFG => (x"0000040000001000"), COMMON_CFG => (x"00000000"), QPLL_CFG => (x"0480181"), QPLL_CLKOUT_CFG => ("0000"), QPLL_COARSE_FREQ_OVRD => ("010000"), QPLL_COARSE_FREQ_OVRD_EN => ('0'), QPLL_CP => ("0000011111"), QPLL_CP_MONITOR_EN => ('0'), QPLL_DMONITOR_SEL => ('0'), QPLL_FBDIV => (QPLL_FBDIV_IN), QPLL_FBDIV_MONITOR_EN => ('0'), QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO), QPLL_INIT_CFG => (x"000006"), QPLL_LOCK_CFG => (x"05E8"), QPLL_LPF => ("1111"), QPLL_REFCLK_DIV => (1), RSVD_ATTR0 => (x"0000"), RSVD_ATTR1 => (x"0000"), QPLL_RP_COMP => ('0'), QPLL_VTRL_RESET => ("00"), RCAL_CFG => ("00") ) port map ( ------------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- DRPADDR => tied_to_ground_vec_i(7 downto 0), DRPCLK => tied_to_ground_i, DRPDI => tied_to_ground_vec_i(15 downto 0), DRPDO => open, DRPEN => tied_to_ground_i, DRPRDY => open, DRPWE => tied_to_ground_i, ---------------------- Common Block - Ref Clock Ports --------------------- GTGREFCLK => tied_to_ground_i, GTNORTHREFCLK0 => tied_to_ground_i, GTNORTHREFCLK1 => tied_to_ground_i, GTREFCLK0 => GT1_GTREFCLK0_COMMON_IN, GTREFCLK1 => tied_to_ground_i, GTSOUTHREFCLK0 => tied_to_ground_i, GTSOUTHREFCLK1 => tied_to_ground_i, ------------------------- Common Block - QPLL Ports ------------------------ BGRCALOVRDENB => tied_to_vcc_i, PMARSVDOUT => open, QPLLDMONITOR => open, QPLLFBCLKLOST => open, QPLLLOCK => GT1_QPLLLOCK_OUT, QPLLLOCKDETCLK => GT1_QPLLLOCKDETCLK_IN, QPLLLOCKEN => tied_to_vcc_i, QPLLOUTCLK => gt1_qplloutclk_i, QPLLOUTREFCLK => gt1_qplloutrefclk_i, QPLLOUTRESET => tied_to_ground_i, QPLLPD => tied_to_ground_i, QPLLREFCLKLOST => GT1_QPLLREFCLKLOST_OUT, QPLLREFCLKSEL => "001", QPLLRESET => GT1_QPLLRESET_IN, QPLLRSVD1 => "0000000000000000", QPLLRSVD2 => "11111", REFCLKOUTMONITOR => open, ----------------------------- Common Block Ports --------------------------- BGBYPASSB => tied_to_vcc_i, BGMONITORENB => tied_to_vcc_i, BGPDB => tied_to_vcc_i, BGRCALOVRD => "00000", PMARSVD => "00000000", RCALENB => tied_to_vcc_i ); end RTL;