----------------------------------------------------------------------------------
--! @file
--! @brief Top-level file
-- Company: McGill University 
-- Engineer: JF Cliche
-- 
-- Create Date:    2013-03-13 
-- Design Name:    chFPGA
-- Module Name:    top - Behavioral 
-- Project Name: Debug
-- Target Devices:  Kintex 7 on KC705 
-- Tool versions:  Vivado 2012.4.1
-- Description: Simulation file that illustrates the problem with Vivadoo Simulator while displaying records.



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---- Package definitions ------------
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package test_package is
	type AXIS32_DAT_STRUCT is -- control/data bus used to communicate from  master to slave
		record
			TVALID: std_logic; -- indicates that the master is driving a valid value
			TDATA : std_logic_vector(31 downto 0); -- data from the master
			TLAST: std_logic; -- indicated that the master is driving the last byte of the frame
			TUSER : std_logic_vector(3 downto 0); -- Used to transfer ancilliary information (overflows, frame info etc). Meaning is specific to each bus segments
		end record;
	type AXIS32_DAT_STRUCT_ARRAY is ARRAY (natural range <>) of AXIS32_DAT_STRUCT;

end test_package;

package body test_package is
end test_package;


-- 
---  LIBRARY DECLARATIONS -------------------------------------------------------------------------------
--! Standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.test_package.all; --! Get all component definitions

entity chFPGA is
end chFPGA;

architecture Behavioral of chFPGA is

component FOO is
    Port ( 
		x: in AXIS32_DAT_STRUCT_ARRAY(1 downto 0)
   	);
end component;

signal TEST_VECTOR: AXIS32_DAT_STRUCT_ARRAY(2 downto 0):=(0=>(TVALID=>'1',TDATA=>X"12345678", TLAST=>'1', TUSER=>"1111"), 1=>(TVALID=>'1',TDATA=>X"12345678", TLAST=>'1', TUSER=>"1111"),2=>(TVALID=>'1',TDATA=>X"12345678", TLAST=>'1', TUSER=>"1111")); -- there is one for each antenna, correlated or not
signal y: AXIS32_DAT_STRUCT_ARRAY(1 downto 0);

begin

y<=TEST_VECTOR(1 downto 0);

FOO0: FOO 
	PORT MAP(
		-- Input interface
		x=> TEST_VECTOR(1 downto 0)
	);

end Behavioral;

---------------------------------------------------------------------
---- FOO entity ------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.test_package.all; --! Get all component definitions

entity FOO is
    Port ( 
		x: in AXIS32_DAT_STRUCT_ARRAY(1 downto 0)
   	);
end FOO;

architecture Behavioral of FOO is
	begin
	end Behavioral;