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uuid:5D20892493BFDB11914A8590D31508C8 Print 7.000000 2.800000 Inches 1 False False Helvetica Helvetica Medium Type 1 003.001 False hv______.PFB; hv______.pfm Cyan Magenta Yellow Black Default Swatch Group 0 White CMYK PROCESS 0.000000 0.000000 0.000000 0.000000 Black CMYK PROCESS 0.000000 0.000000 0.000000 100.000000 CMYK Red CMYK PROCESS 0.000000 100.000000 100.000000 0.000000 CMYK Yellow CMYK PROCESS 0.000000 0.000000 100.000000 0.000000 CMYK Green CMYK PROCESS 100.000000 0.000000 100.000000 0.000000 CMYK Cyan CMYK PROCESS 100.000000 0.000000 0.000000 0.000000 CMYK Blue CMYK PROCESS 100.000000 100.000000 0.000000 0.000000 CMYK Magenta CMYK PROCESS 0.000000 100.000000 0.000000 0.000000 C=15 M=100 Y=90 K=10 CMYK PROCESS 14.999998 100.000000 90.000004 10.000002 C=0 M=90 Y=85 K=0 CMYK PROCESS 0.000000 90.000004 84.999996 0.000000 C=0 M=80 Y=95 K=0 CMYK PROCESS 0.000000 80.000001 94.999999 0.000000 C=0 M=50 Y=100 K=0 CMYK PROCESS 0.000000 50.000000 100.000000 0.000000 C=0 M=35 Y=85 K=0 CMYK PROCESS 0.000000 35.000002 84.999996 0.000000 C=5 M=0 Y=90 K=0 CMYK PROCESS 5.000001 0.000000 90.000004 0.000000 C=20 M=0 Y=100 K=0 CMYK PROCESS 19.999999 0.000000 100.000000 0.000000 C=50 M=0 Y=100 K=0 CMYK PROCESS 50.000000 0.000000 100.000000 0.000000 C=75 M=0 Y=100 K=0 CMYK PROCESS 75.000000 0.000000 100.000000 0.000000 C=85 M=10 Y=100 K=10 CMYK PROCESS 84.999996 10.000002 100.000000 10.000002 C=90 M=30 Y=95 K=30 CMYK PROCESS 90.000004 30.000001 94.999999 30.000001 C=75 M=0 Y=75 K=0 CMYK PROCESS 75.000000 0.000000 75.000000 0.000000 C=80 M=10 Y=45 K=0 CMYK PROCESS 80.000001 10.000002 44.999999 0.000000 C=70 M=15 Y=0 K=0 CMYK PROCESS 69.999999 14.999998 0.000000 0.000000 C=85 M=50 Y=0 K=0 CMYK PROCESS 84.999996 50.000000 0.000000 0.000000 C=100 M=95 Y=5 K=0 CMYK PROCESS 100.000000 94.999999 5.000001 0.000000 C=100 M=100 Y=25 K=25 CMYK PROCESS 100.000000 100.000000 25.000000 25.000000 C=75 M=100 Y=0 K=0 CMYK PROCESS 75.000000 100.000000 0.000000 0.000000 C=50 M=100 Y=0 K=0 CMYK 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(M4.9.61823.T0..TableTitle.Table.2.General.Recommended.Operating.Conditions) 4053 0 R (M4.9.61874.TableNoteNumberedCont.4.Some.jitter.and.dutycycle.specifications.include.1.of.input.clock) 4054 0 R (M4.9.63003.TableNoteNumberedCont.3.Input.registers.AREG.or.BREG.are.typically.used.when.inferring.a.) 4055 0 R (M4.9.63039.TableNoteNumbered.1.Each.of.the.User.IO.and.DualPurpose.pins.is.associated.with.one.of.th) 4056 0 R (M4.9.63395.XTitleDocType.Product.Specification) 4057 0 R (M4.9.63919.TableTitle.Table.38.CCLK.Characteristics.by.ConfigRate.Option.Setting) 4058 0 R (M4.9.64277.TableTitle.Table.119.Configuration.Timing.Requirements.for.Attached.SPI.Serial.Flash) 4059 0 R (M4.9.64507.TableNoteNumberedCont.2.This.time.requires.adjustment.whenever.a.signal.standard.other.th) 4060 0 R (M4.9.65179.Heading3.Serial.Peripheral.Interface.SPI.Configuration.Timing) 4061 0 R (M4.9.65552.T0..TableTitle.Table.11.PintoPin.ClocktoOutput.and.Data.Valid.Times.for.the.IOB.Output.Pa) 4062 0 R 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(M5.9.33179.TableNoteNumberedCont.2.DAThe.eight.global.clock.pins.in.this.bank.have.op)] /Names [(M4.9.67300.TableNoteNumberedCont.3.CLKIN.input.jitter.beyond.these.limits.may.cause.the.DCM.to.lose.) 3937 0 R (M4.9.68193.TableNoteNumberedCont.4.There.is.approximately.100mV.of.hysteresis.on.inputs.using.LVCMOS) 3938 0 R (M4.9.68530.TableNoteNumberedCont.4.CLKIN.input.jitter.beyond.these.limits.might.cause.the.DCM.to.los) 3939 0 R (M4.9.70522.TableNoteNumberedCont.3.According.to.the.PCI.specification) 3940 0 R (M4.9.71084.TableNoteNumbered.1.This.VCCO.range.spans.the.lowest.and.highest.operating.voltages.for.a) 3941 0 R (M4.9.71642.T0..TableTitle.Table.32.Switching.Characteristics.for.the.PS) 3942 0 R (M4.9.72478.T0..TableTitle.Table.14.Setup.and.Hold.Times.for.the.IOB.Input.Path) 3943 0 R (M4.9.72603.TableNoteNumberedCont.2.This.propagation.time.requires.adjustment.whenever.a.signal.stand) 3944 0 R (M4.9.72865.TableNoteNumberedCont.4.To.support.double.the.maximum.effective.FCLKIN.limit.set.the.CLKI) 3945 0 R (M4.9.73142.XAnchorFigure.XRef.Target..Figure.76) 3946 0 R (M4.9.73149.TableNoteNumberedCont.2.Each.of.the.User.IO.and.DualPurpose.pins.is.associated.with.one.o) 3947 0 R (M4.9.74136.XAnchorFigure.XRef.Target..Figure.77) 3948 0 R (M4.9.77209.TableNoteNumberedCont.3.These.hold.times.require.adjustment.whenever.a.signal.standard.ot) 3949 0 R (M4.9.77465.T0..TableTitle.Table.14.PintoPin.Setup.and.Hold.Times.for.the.IOB.Input.Path.Continued) 3950 0 R (M4.9.77747.TableNoteNumberedCont.3.To.support.double.the.maximum.effective.FCLKIN.limit.set.the.CLKI) 3951 0 R (M4.9.78663.TableTitle.Table.115.Timing.for.Bytewide.Peripheral.Interface.BPI.Configuration.Mode.Cont) 3952 0 R (M4.9.79682.TableNoteNumberedCont.6.For.information.on.PCI.IP.solutions.see.wwwxilinxcompci.The.PCIX.) 3953 0 R (M4.9.79797.TableTitle.Table.95.CLB.Shift.Register.Switching.Characteristics) 3954 0 R (M4.9.80860.TableNoteNumberedCont.2.For.serial.configuration.with.a.daisychain.of.multiple.FPGAs.the.) 3955 0 R (M4.9.81527.TableNoteNumberedCont.2.This.parameter.is.based.on.characterization.The.pullup.resistance) 3956 0 R (M4.9.82044.TableNoteNumberedCont.3.For.device.operation.the.maximum.signal.voltage.VIH.max.may.be.as) 3957 0 R (M4.9.82413.TableNoteNumberedCont.4.Tested.according.to.the.relevant.PCI.specifications.For) 3958 0 R (M4.9.83065.T0..TableTitle.Table.17.Timing.for.the.IOB.ThreeState.Path) 3959 0 R (M4.9.84683.TableNoteNumberedCont.4.See.XAPP459.Eliminating.IO.Coupling.Effects.when.Interfacing.Larg) 3960 0 R (M4.9.84839.TableNoteNumberedCont.4.DCM.output.jitter.is.included.in.all.measurements) 3961 0 R (M4.9.85002.T0..TableTitle.Table.9.Recommended.Operating.Conditions.for.IO.Using.DifferentialEnded.St) 3962 0 R (M4.9.85195.TableNoteNumberedCont.2.For.optimal.jitter.tolerance.and.faster.lock.time.use.the.CLKINPE) 3963 0 R (M4.9.85475.H1..Heading1.DC.Electrical.Characteristics) 3964 0 R (M4.9.85752.TableNoteNumberedCont.3.The.initial.BYTE.timing.can.be.extended.using.an.external.appropr) 3965 0 R (M4.9.85894.TableNoteNumberedCont.2.Quiescent.supply.current.is.measured.with.all.IO.drivers.in.a.hig) 3966 0 R (M4.9.86882.TableTitle.Table.74.Supply.Voltage.Ramp.Rate) 3967 0 R (M4.9.87830.T0..TableTitle.Table.14.Timing.for.the.Master.and.Slave.Parallel.Configuration.Modes) 3968 0 R (M4.9.88449.TableNoteNumberedCont.3.All.Dedicated.pins.PROGB.DONE.TCK.TDI.TDO.and.TMS.draw.power.from) 3969 0 R (M4.9.89390.DocumentTitleSub.DC.and.Switching.Characteristics) 3970 0 R (M4.9.89620.TableNoteNumberedCont.3) 3971 0 R (M4.9.91940.T0..TableTitle.Table.37.Timing.for.the.JTAG.Test.Access.Port) 3972 0 R (M4.9.93653.TableTitle.Table.3.Power.Voltage.Levels.Necessary.for.Preserving.RAM.Contents) 3973 0 R (M4.9.94416.TableNoteNumberedCont.3.For.the.LVCMOS.and.LVTTL.standards.the.same.VOL.and.VOH) 3974 0 R (M4.9.95912.PageCount.8) 3975 0 R (M4.9.97982.TableTitle.Table.39.Master.Mode.CCLK.Minimum.Low.and.High.Time) 3976 0 R (M5.8.newlink.CLKType) 3977 0 R (M5.8.newlink.CONFIGType) 3978 0 R (M5.8.newlink.DUALType) 3979 0 R (M5.8.newlink.INPUTType) 3980 0 R (M5.8.newlink.IOType) 3981 0 R (M5.8.newlink.JTAGType) 3982 0 R (M5.8.newlink.VREFType) 3983 0 R (M5.9.14742.TableNoteNumbered.1.Some.VREF.pins.are.on.INPUT.pins.See.pinout.tables.for.details) 3984 0 R (M5.9.15572.DocumentTitleSub.Pinout.Descriptions) 3985 0 R (M5.9.15984.TableTitle.Table.20.User.IOs.Per.Bank.on.XC3S1200E.in.the.FT256.Package) 3986 0 R (M5.9.18367.TableTitle.Table.23.User.IOs.Per.Bank.for.XC3S500E.in.FG320.Package) 3987 0 R (M5.9.19017.XAnchorFigure.XRef.Target..Figure.86) 3988 0 R (M5.9.19913.XAnchorFigure.XRef.Target..Figure.87) 3989 0 R (M5.9.20307.Heading2.Package.Thermal.Characteristics) 3990 0 R (M5.9.21459.TableNoteNumbered.1.Some.VREF.and.CLK.pins.are.on.INPUT.pins) 3991 0 R (M5.9.21548.TableNoteNumbered.1.See.the.package.material.declaration.data.sheet.fo) 3992 0 R (M5.9.24662.TableTitle.Table.5.Power.and.Ground.Supply.Pins.by.Package) 3993 0 R (M5.9.26556.XAnchorFigure.XRef.Target..Figure.83) 3994 0 R (M5.9.27541.TableTitle.Table.3.FG400.Package.Pinout) 3995 0 R (M5.9.27668.TableNoteNumbered.1.Some.VREF.and.CLK.pins.are.on.INPUT.pins) 3996 0 R (M5.9.27896.TableTitle.Table.3.QFP.and.BGA.Comparison) 3997 0 R (M5.9.28718.TableTitle.Table.5.FG484.Package.Pinout) 3998 0 R (M5.9.30620.TableNoteNumberedCont.2.The.eight.global.clock.pins.in.this.bank.have.optional.functional) 3999 0 R (M5.9.33179.TableNoteNumberedCont.2.DAThe.eight.global.clock.pins.in.this.bank.have.op) 4000 0 R] >> endobj 3644 0 obj << /Limits [(M5.9.33247.TableNoteNumberedCont.2.The.eight.global.clock.pins.in.this.bank.have.optional.functional) (P.102C3)] /Names [(M5.9.33247.TableNoteNumberedCont.2.The.eight.global.clock.pins.in.this.bank.have.optional.functional) 3873 0 R (M5.9.33545.TableNoteNumberedCont.2.The.eight.global.clock.pins.in.this.bank.have.optional.functional) 3874 0 R (M5.9.33592.TableNoteNumberedCont.2.All.devices.have.24.possible.global.clock.and.right.and.lefthalf.) 3875 0 R (M5.9.34009.TableTitle.Table.4.User.IOs.Per.Bank.for.the.XC3S250E.and.XC3S500E.in.the.FG400.Package) 3876 0 R (M5.9.34387.TableNoteNumbered.1...IO.bank.number.an.integer.between.0.and.3) 3877 0 R (M5.9.34768.TableNoteNumbered.1.Some.VREF.and.CLK.pins.are.on.INPUT.pins) 3878 0 R (M5.9.36721.TableTitle.Table.130.TQ144.Footprint.Migration.Differences) 3879 0 R (M5.9.36766.TableTitle.Table.2.Spartan3E.Family.Package.Options) 3880 0 R (M5.9.37699.TableNoteNumberedCont.2.The.eight.global.clock.pins.in.this.bank.have.optional.functional) 3881 0 R (M5.9.38024.TableTitle.Table.11.User.IOs.Per.Bank.for.the.XC3S100E.in.TQ144.Package) 3882 0 R (M5.9.38885.XAnchorFigure.XRef.Target..Figure.80) 3883 0 R (M5.9.39680.TableTitle.Table.24.User.IOs.Per.Bank.for.XC3S1200E.in.FG320.Package) 3884 0 R (M5.9.40999.Heading1Wide.Notice.of.Disclaimer) 3885 0 R (M5.9.41608.TableTitle.Table.18.User.IOs.Per.Bank.on.XC3S250E.in.the.FT256.Package) 3886 0 R (M5.9.49563.TableNoteNumbered.1.Some.VREF.and.CLK.pins.are.on.INPUT.pins) 3887 0 R (M5.9.50126.TableNoteNumberedCont.2.The.eight.global.clock.pins.in.this.bank.have.optional.functional) 3888 0 R (M5.9.51460.TableTitle.Table.15.PQ208.Package.Pinout) 3889 0 R (M5.9.55748.TableNoteNumberedCont.2.The.eight.global.clock.pins.in.this.bank.have.opti) 3890 0 R (M5.9.56744.TableTitle.Table.17.FT256.Footprint.Migration.Differences) 3891 0 R (M5.9.60072.TableTitle.Table.12.User.IOs.Per.Bank.for.the.XC3S250E.in.TQ144.Package) 3892 0 R (M5.9.61306.TableTitle.Table.6.User.IOs.Per.Bank.for.the.XC3S1600E.in.the.FG484.Package) 3893 0 R (M5.9.63082.TableNoteNumbered.1.Some.VREF.and.CLK.pins.are.on.INPUT.pins) 3894 0 R (M5.9.63350.TableTitle.Table.10.TQ144.Package.Pinout) 3895 0 R (M5.9.63395.XTitleDocType.Product.Specification) 3896 0 R (M5.9.63512.TableTitle.Table.13.TQ144.Footprint.Migration.Differences) 3897 0 R (M5.9.65693.TableTitle.Table.6.Maximum.User.IO.by.Package) 3898 0 R (M5.9.66884.TableNoteNumbered.1.Some.VREF.and.CLK.pins.are.on.INPUT.pins) 3899 0 R (M5.9.68720.TableNoteNumberedCont.2.The.eight.global.clock.pins.in.this.bank.have.optional.functional) 3900 0 R (M5.9.69824.TableTitle.Table.128.User.IOs.Per.Bank.for.the.XC3S250E.and.XC3S500E.in.the.CP132.Package) 3901 0 R (M5.9.70786.TableNoteNumberedCont.2.The.eight.global.clock.pins.in.this.bank.have.optional.functional) 3902 0 R (M5.9.72088.TableNoteNumberedCont.2.The.eight.global.clock.pins.in.this.bank.have.optional.functional) 3903 0 R (M5.9.72839.Version.DS099.30.September.14.2010) 3904 0 R (M5.9.73344.XAnchorFigure.XRef.Target..Figure.81) 3905 0 R (M5.9.73982.TableTitle.Table.1.Types.of.Pins.on.Spartan3E.FPGAs) 3906 0 R (M5.9.74019.XAnchorFigure.XRef.Target..Figure.85) 3907 0 R (M5.9.74263.TableTitle.Table.8.User.IOs.Per.Bank.for.XC3S100E.and.XC3S250E.in.VQ100.Package) 3908 0 R (M5.9.74547.TableNoteNumbered.1.Some.VREF.and.CLK.pins.are.on.INPUT.pins) 3909 0 R (M5.9.74744.TableNoteNumberedCont.2.The.eight.global.clock.pins.in.this.bank.have.optional.functional) 3910 0 R (M5.9.78690.TableTitle.Table.19.User.IOs.Per.Bank.on.XC3S500E.in.the.FT256.Package) 3911 0 R (M5.9.81790.TableNoteNumbered.1.Some.VREF.and.CLK.pins.are.on.INPUT.pins) 3912 0 R (M5.9.82555.TableNoteNumberedCont.2.The.eight.global.clock.pins.in.this.bank.have.optional.functional) 3913 0 R (M5.9.83414.Heading2.Mechanical.Drawings) 3914 0 R (M5.9.85006.XAnchorFigure.XRef.Target..Figure.79) 3915 0 R (M5.9.85796.TableNoteNumbered.1.Some.VREF.and.CLK.pins.are.on.INPUT.pins) 3916 0 R (M5.9.86361.TableNoteNumberedCont.2.The.eight.global.clock.pins.in.this.bank.have.optional.functional) 3917 0 R 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(M5.9.99311.TableTitle.Table.21.FG320.Package.Pinout) 3931 0 R (M5.9.OLELINK2) 3932 0 R (M5.9.Ref89501097) 3933 0 R (P.100C3) 3934 0 R (P.101C3) 3935 0 R (P.102C3) 3936 0 R] >> endobj 3645 0 obj << /Limits [(P.103C3) (P.160C5)] /Names [(P.103C3) 3809 0 R (P.104C3) 3810 0 R (P.105C3) 3811 0 R (P.106C3) 3812 0 R (P.107C3) 3813 0 R (P.108C3) 3814 0 R (P.109C3) 3815 0 R (P.10C3) 3816 0 R (P.110C3) 3817 0 R (P.111C3) 3818 0 R (P.112C3) 3819 0 R (P.113C3) 3820 0 R (P.114C3) 3821 0 R (P.115C4) 3822 0 R (P.116C4) 3823 0 R (P.117C4) 3824 0 R (P.118C4) 3825 0 R (P.119C4) 3826 0 R (P.11C3) 3827 0 R (P.120C4) 3828 0 R (P.121C4) 3829 0 R (P.122C4) 3830 0 R (P.123C4) 3831 0 R (P.124C4) 3832 0 R (P.125C4) 3833 0 R (P.126C4) 3834 0 R (P.127C4) 3835 0 R (P.128C4) 3836 0 R (P.129C4) 3837 0 R (P.12C3) 3838 0 R (P.130C4) 3839 0 R (P.131C4) 3840 0 R (P.132C4) 3841 0 R (P.133C4) 3842 0 R (P.134C4) 3843 0 R (P.135C4) 3844 0 R (P.136C4) 3845 0 R (P.137C4) 3846 0 R (P.138C4) 3847 0 R (P.139C4) 3848 0 R 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