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Subsystem v2.0 Product Guide (PG203) Xilinx, Inc. Provides a high performance, low latency 100 Gb/s Ethernet port that allows for a wide range of user customization and statistics gathering. The dedicated block provides both the 100G MAC and PCS logic with support for IEEE 1588-2008 two-step hardware timestamping. 2016-12-02T10:31:51Z FrameMaker 2015.0.5 Acrobat Distiller 15.0 (Windows) Virtex UltraScale+,ultrascale+,rs-fec, segmented LBUS, Vivado Design Suite, QuestaSim, XDC, CAUI, IEEE 1588 v2 PTP, IEEE 802.3bd,IEEE 802.3ba,pg165 uuid:9698057e-b4d9-4e3e-b350-78c73c123007 uuid:308af42d-377f-47ac-a694-3493892da99c 2016-12-05T15:01:06+07:00 endstream endobj 12968 0 obj << /Author (Xilinx, Inc.) /CreationDate (D:20161202103151Z) /Creator (FrameMaker 2015.0.5) /Keywords (Virtex UltraScale+,ultrascale+,rs-fec, segmented LBUS, Vivado Design Suite, QuestaSim, XDC, CAUI, IEE\ E 1588 v2 PTP, IEEE 802.3bd,IEEE 802.3ba,pg165) /ModDate (D:20161205150106+07'00') /Producer (Xilinx, Inc. via ABCpdf) /Subject (Provides a high performance, low latency 100 Gb/s Ethernet port that allows for a wide range of user \ customization and statistics gathering. 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00000 n 0004360782 00000 n 0004360941 00000 n 0004361101 00000 n 0004361281 00000 n 0004361450 00000 n 0004361619 00000 n 0004361788 00000 n 0004361957 00000 n 0004362126 00000 n 0004362295 00000 n 0004362464 00000 n 0004362633 00000 n 0004362802 00000 n 0004362971 00000 n 0004363090 00000 n 0004363259 00000 n 0004363428 00000 n 0004363597 00000 n 0004363720 00000 n 0004363768 00000 n 0004364331 00000 n 0004364609 00000 n 0004367546 00000 n 0004368296 00000 n 0004368367 00000 n trailer << /Size 12971 >> startxref 192 %%EOF 12967 0 obj <>stream application/pdf UltraScale+ Devices Integrated 100G Ethernet Subsystem v2.1 Product Guide (PG203) Xilinx, Inc. Provides a high performance, low latency 100 Gb/s Ethernet port that allows for a wide range of user customization and statistics gathering. The dedicated block provides both the 100G MAC and PCS logic with support for IEEE 1588-2008 two-step hardware timestamping. Virtex UltraScale+,ultrascale+,rs-fec, segmented LBUS, Vivado Design Suite, QuestaSim, XDC, CAUI, IEEE 1588 v2 PTP, IEEE 802.3bd,IEEE 802.3ba,pg165 2016-12-02T10:31:51Z FrameMaker 2015.0.5 2016-12-05T15:01:44-07:00 2016-12-05T15:01:44-07:00 Xilinx, Inc. via ABCpdf "Virtex UltraScale+,ultrascale+,rs-fec, segmented LBUS, Vivado Design Suite, QuestaSim, XDC, CAUI, IEEE 1588 v2 PTP, IEEE 802.3bd,IEEE 802.3ba,pg165" uuid:9698057e-b4d9-4e3e-b350-78c73c123007 uuid:a030ebec-bd24-40f8-be9e-f91ab9825733 PG203 endstream endobj 13171 0 obj <> endobj xref 0 1 0000000000 65535 f 12967 1 0004627942 00000 n 13171 1 0004632524 00000 n trailer <<2EA42A265E64EA45B7DA096EB93BE676>]/Prev 192>> startxref 4633245 %%EOF