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The core is a scalable chip-to-chip interconnect protocol designed to enable the following for use in select UltraScale™ and UltraScale+™ architectures. Integrated Interlaken 150G v2.2 LogiCORE IP Product Guide (PG169) 2017-05-24T02:50:38Z FrameMaker 2015.0.5 2017-05-24T03:28:02-07:00 Acrobat Distiller 15.0 (Windows) pg169,Virtex UltraScale,segmented LBUS,LBUS,interconnect protocol,Vivado,Questa SIM,XDC,GTY,GTH,IP catalog,BurstMax,BurstShort,169, Virtex UltraScale, Kintex UltraScale,Virtex UltraScale+, Kintex UltraScale+,Zynq uuid:ca7acd9c-37b5-4bc8-82b1-bd5356bd80cc uuid:ce1752c1-77d8-4b97-8e46-72161b0dc50f 2017-05-24T03:38:47+07:00 endstream endobj 8394 0 obj << /Author (Xilinx, Inc.) /CreationDate (D:20170524025038Z) /Creator (FrameMaker 2015.0.5) /Keywords (pg169,Virtex UltraScale,segmented LBUS,LBUS,interconnect protocol,Vivado,Questa SIM,XDC,GTY,GTH,IP ca\ talog,BurstMax,BurstShort,169, Virtex UltraScale, Kintex UltraScale,Virtex UltraScale+, Kintex UltraS\ cale+,Zynq) /ModDate (D:20170524033847+07'00') /Producer (Xilinx, Inc. via ABCpdf) /Subject (The core is a scalable chip-to-chip interconnect protocol designed to enable the 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