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(unique_47_Connect_42_section_N10011_N1000E_N10001) 593 0 R (unique_47_Connect_42_ul_uv3_qxb_wy) 594 0 R (unique_47_Connect_42_ul_v3b_5xb_wy) 595 0 R (unique_48) 597 0 R (unique_48_Connect_42_note_N10087_N10079_N10055_N10011_N1000F_N10001) 601 0 R (unique_48_Connect_42_ol_hb4_qck_nx) 600 0 R (unique_48_Connect_42_section_N10010_N1000E_N10001) 599 0 R (unique_49) 602 0 R (unique_49_Connect_42_p_bym_jpw_xcb) 605 0 R (unique_49_Connect_42_section_N10011_N1000F_N10001) 604 0 R (unique_49_Connect_42_table_sld_cf5_wcb) 606 0 R (unique_4_Connect_42_fig_dr3_l3r_4cb) 436 0 R (unique_4_Connect_42_fig_gml_gmf_rhb) 438 0 R (unique_4_Connect_42_fig_m22_mnf_rhb) 442 0 R (unique_4_Connect_42_fig_wtv_q3r_4cb) 440 0 R (unique_4_Connect_42_image_gm1_ktr_4cb) 441 0 R (unique_4_Connect_42_image_is1_qrf_rhb) 443 0 R (unique_4_Connect_42_image_ojz_5sr_4cb) 437 0 R (unique_4_Connect_42_image_x21_3nf_rhb) 439 0 R (unique_4_Connect_42_ul_s4d_lmq_4cb) 435 0 R (unique_5) 444 0 R (unique_50) 607 0 R (unique_50_Connect_42_section_N10011_N1000E_N10001) 609 0 R (unique_50_Connect_42_section_nd1_sk2_sy) 610 0 R (unique_50_Connect_42_section_x4j_fpk_3y) 611 0 R (unique_6) 446 0 R (unique_7) 448 0 R (unique_7_Connect_42_section_bhk_sfg_qy) 450 0 R (unique_8) 451 0 R (unique_9) 454 0 R (unique_9_Connect_42_ad287312) 453 0 R (unique_9_Connect_42_section_N10011_N1000F_N10001) 456 0 R] >> endobj 618 0 obj << /Author (Xilinx, Inc.) /CreationDate (D:20191029195220-08'00') /Creator (AH XSL Formatter V6.6 MR2 for Linux64 : 6.6.4.36256 \(2018/11/29 19:37JST\)) /Keywords (axi, verification, ip, reset, vip, UltraScale, UltraScale+, zynq-7000, SoC, 7 series, verilog) /ModDate (D:20191029195358+07'00') /PostProcess (v2019.2.0.1) /Producer (Xilinx, Inc. via ABCpdf) /Subject (This document describes the Reset Verification IP \(VIP\) core that supports simulation of customer-d\ esigned test bench or design which requires a reset signal.) /Title (Reset Verification IP v1.0 LogiCORE IP Product Guide) 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