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The IP provides an optional AXI4 or AXI4-Stream user interface. PCIe DMA Subsystem v2.0 Product Guide (PG195) Xilinx, Inc. Acrobat Distiller 15.0 (Windows) UltraScale, UltraScale+,Virtex-7,v-7,v7,AXI4,AXI4-Lite,AXI4-Stream,memory mapped,C2H,H2C,endpoint,xdma uuid:15ae8fb7-34f6-4be2-9d22-876ac467f9ee uuid:8ac5e6c5-6744-4fb0-98ce-93e8e979b202 2016-06-01T08:28:21+01:00 endstream endobj 4717 0 obj << /Author (Xilinx, Inc.) /CreationDate (D:20160601080152Z) /Creator (FrameMaker 2015) /Keywords (UltraScale, UltraScale+,Virtex-7,v-7,v7,AXI4,AXI4-Lite,AXI4-Stream,memory mapped,C2H,H2C,endpoint,xdm\ a) /ModDate (D:20160601082821+01'00') /Producer (Xilinx, Inc. via ABCpdf) /Subject (The Xilinx® DMA Subsystem for PCI Express® implements a high performance, configurable Scatte\ r Gather DMA for use with the PCI Express 3.x/4.x Integrated Block. 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