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The Xilinx&reg; DMA Subsystem for PCI Express&reg; implements a high performance, configurable Scatter Gather DMA for use with the PCI Express 3.x/4.x Integrated Block. The IP provides an optional AXI4 or AXI4-Stream user interface. DMA/Bridge Subsystem for PCI Express v3.1 Product Guide (PG195) 2017-06-15T15:56:44Z FrameMaker 2015.0.5 Acrobat Distiller 15.0 (Windows) UltraScale, UltraScale+,Virtex-7,v-7,v7,AXI4,AXI4-Lite,AXI4-Stream,memory mapped,C2H,H2C,endpoint,xdma uuid:cd6923bf-aee0-48c8-80f3-b13fab5fa3d2 uuid:41ed03a7-24e9-469e-a061-95211c0dbffa 2017-06-15T17:32:51+06:00 endstream endobj 6500 0 obj << /Author (Xilinx, Inc.) /CreationDate (D:20170615155644Z) /Creator (FrameMaker 2015.0.5) /Keywords (UltraScale, UltraScale+,Virtex-7,v-7,v7,AXI4,AXI4-Lite,AXI4-Stream,memory mapped,C2H,H2C,endpoint,xdm\ a) /ModDate (D:20170615173251+06'00') /Producer (Xilinx, Inc. via ABCpdf) /Subject (The Xilinx® DMA Subsystem for PCI Express® implements a high performance, configurable Scatte\ r Gather DMA for use with the PCI Express 3.x/4.x Integrated Block. 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