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>> endobj 4702 0 obj << /D [944 0 R /XYZ 224 227 null] >> endobj 4703 0 obj << /D [944 0 R /XYZ 284 227 null] >> endobj 4704 0 obj << /D [944 0 R /XYZ 92 264 null] >> endobj 4705 0 obj << /D [944 0 R /XYZ 92 205 null] >> endobj 4706 0 obj << /D [944 0 R /XYZ 92 179 null] >> endobj 4707 0 obj << /D [944 0 R /XYZ 92 160 null] >> endobj 4708 0 obj << /D [944 0 R /XYZ 139 160 null] >> endobj 4709 0 obj << /D [944 0 R /XYZ 216 160 null] >> endobj 4710 0 obj << /D [944 0 R /XYZ 273 160 null] >> endobj 4711 0 obj << /D [944 0 R /XYZ 92 140 null] >> endobj 4712 0 obj << /D [944 0 R /XYZ 139 140 null] >> endobj 4713 0 obj << /D [944 0 R /XYZ 216 140 null] >> endobj 4714 0 obj << /D [944 0 R /XYZ 273 140 null] >> endobj 4715 0 obj << /D [944 0 R /XYZ 92 178 null] >> endobj 4716 0 obj << /D [951 0 R /XYZ 92 724 null] >> endobj 4717 0 obj << /D [951 0 R /XYZ 92 698 null] >> endobj 4718 0 obj << /D [951 0 R /XYZ 92 679 null] >> endobj 4719 0 obj << /D [951 0 R /XYZ 143 679 null] >> endobj 4720 0 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/XYZ 214 333 null] >> endobj 4739 0 obj << /D [937 0 R /XYZ 269 333 null] >> endobj 4740 0 obj << /D [937 0 R /XYZ 92 313 null] >> endobj 4741 0 obj << /D [937 0 R /XYZ 139 313 null] >> endobj 4742 0 obj << /D [937 0 R /XYZ 214 313 null] >> endobj 4743 0 obj << /D [937 0 R /XYZ 269 313 null] >> endobj 4744 0 obj << /D [937 0 R /XYZ 92 351 null] >> endobj 4745 0 obj << /D [937 0 R /XYZ 92 291 null] >> endobj 4746 0 obj << /D [937 0 R /XYZ 92 265 null] >> endobj 4747 0 obj << /D [937 0 R /XYZ 92 246 null] >> endobj 4748 0 obj << /D [937 0 R /XYZ 136 246 null] >> endobj 4749 0 obj << /D [937 0 R /XYZ 207 246 null] >> endobj 4750 0 obj << /D [937 0 R /XYZ 259 246 null] >> endobj 4751 0 obj << /D [937 0 R /XYZ 92 227 null] >> endobj 4752 0 obj << /D [937 0 R /XYZ 136 227 null] >> endobj 4753 0 obj << /D [937 0 R /XYZ 207 227 null] >> endobj 4754 0 obj << /D [937 0 R /XYZ 259 227 null] >> endobj 4755 0 obj << /D [937 0 R /XYZ 92 264 null] >> endobj 4756 0 obj << /D [937 0 R /XYZ 92 205 null] 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/XYZ 187 313 null] >> endobj 4794 0 obj << /D [930 0 R /XYZ 230 313 null] >> endobj 4795 0 obj << /D [930 0 R /XYZ 92 351 null] >> endobj 4796 0 obj << /D [930 0 R /XYZ 92 291 null] >> endobj 4797 0 obj << /D [930 0 R /XYZ 92 265 null] >> endobj 4798 0 obj << /D [930 0 R /XYZ 92 246 null] >> endobj 4799 0 obj << /D [930 0 R /XYZ 130 246 null] >> endobj 4800 0 obj << /D [930 0 R /XYZ 191 246 null] >> endobj 4801 0 obj << /D [930 0 R /XYZ 236 246 null] >> endobj 4802 0 obj << /D [930 0 R /XYZ 92 227 null] >> endobj 4803 0 obj << /D [930 0 R /XYZ 130 227 null] >> endobj 4804 0 obj << /D [930 0 R /XYZ 191 227 null] >> endobj 4805 0 obj << /D [930 0 R /XYZ 236 227 null] >> endobj 4806 0 obj << /D [930 0 R /XYZ 92 264 null] >> endobj 4807 0 obj << /D [930 0 R /XYZ 92 205 null] >> endobj 4808 0 obj << /D [930 0 R /XYZ 92 179 null] >> endobj 4809 0 obj << /D [930 0 R /XYZ 92 160 null] >> endobj 4810 0 obj << /D [930 0 R /XYZ 128 160 null] >> endobj 4811 0 obj << /D [930 0 R /XYZ 187 160 null] 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n\000s) >> endobj 8952 0 obj << /Length 3039 /Subtype /XML /Type /Metadata >> stream FrameMaker 2015.2 2016-04-08T18:33:52Z 2015 Acrobat Distiller 15.0 (Windows) pcs, mac, 25, vivado,Virtex UltraScale,LBUS,XGML,XXVMII,PMA,XDC,UltraScale+, Virtex UltraScale, Kintex UltraScale,Virtex UltraScale+, Kintex UltraScale+,Zynq UltraScale+ MPSoC,XGMII,XXVMII application/pdf 10G/25G High Speed Ethernet Subsystem v1.2 Product Guide (PG210) Xilinx, Inc. This subsystem implements the 25G Ethernet Media Access Controller (MAC) with a Physical Coding Sublayer (PCS) as specified by the 25G Ethernet Consortium. MAC and PCS/PMA or PCS/PMA alone are available. Legacy operation at 10 Gb/s is supported. The subsystem is delivered as a netlist targeted for Xilinx devices. 2015 uuid:13da9c47-7359-42d2-ae59-3462a766f38c uuid:2297ef23-6d03-48f4-b126-8d19ca35a989 2016-04-08T22:05:37+07:00 endstream endobj 8953 0 obj << /Author (Xilinx, Inc.) /Copyright (2015) /CreationDate (D:20160408183352Z) /Creator (FrameMaker 2015.2) /Keywords (pcs, mac, 25, vivado,Virtex UltraScale,LBUS,XGML,XXVMII,PMA,XDC,UltraScale+, Virtex UltraScale, Kinte\ x UltraScale,Virtex UltraScale+, Kintex UltraScale+,Zynq UltraScale+ MPSoC,XGMII,XXVMII) /ModDate (D:20160408220537+07'00') /Producer (Xilinx, Inc. via ABCpdf) /Subject (This subsystem implements the 25G Ethernet Media Access Controller \(MAC\) with a Physical Coding Sub\ layer \(PCS\) as specified by the 25G Ethernet Consortium. MAC and PCS/PMA or PCS/PMA alone are avail\ able. Legacy operation at 10 Gb/s is supported. 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