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For each property this manual provides a description; supported Xilinx® FPGA devices; applicable logic elements or device resources; accepted values; Verilog, VHDL, and XDC syntax examples; and affected FPGA design flow steps. Vivado Design Suite Properties Reference Guide Xilinx, Inc. Acrobat Distiller 17.0 (Windows) ug912,Virtex,Kintex,Artix,properties,Xilinx Design constraints,XDC,XDC properties,architecture support, applicable elements,propagation rules,properties values,syntax examples 2013-2020 2013-2020 uuid:af1bba80-5136-4b78-829d-2818c4745fe3 uuid:d7fb97e8-a86f-42bc-9f03-51c875294fa8 2021-02-10T15:30:39+07:00 endstream endobj 5527 0 obj << /Kids [5528 0 R 5529 0 R 5530 0 R 5531 0 R 5532 0 R 5533 0 R 5534 0 R 5535 0 R 5536 0 R 5537 0 R 5538 0 R 5539 0 R 5540 0 R 5541 0 R 5542 0 R 5543 0 R 5544 0 R 5545 0 R 5546 0 R 5547 0 R 5548 0 R 5549 0 R 5550 0 R 5551 0 R 5552 0 R 5553 0 R 5554 0 R 5555 0 R 5556 0 R 5557 0 R 5558 0 R 5559 0 R 5560 0 R 5561 0 R 5562 0 R 5563 0 R 5564 0 R 5565 0 R 5566 0 R 5567 0 R 5568 0 R 5569 0 R 5570 0 R 5571 0 R 5572 0 R 5573 0 R 5574 0 R 5575 0 R 5576 0 R 5577 0 R 5578 0 R 5579 0 R 5580 0 R 5581 0 R 5582 0 R 5583 0 R 5584 0 R 5585 0 R 5586 0 R 5587 0 R 5588 0 R 5589 0 R 5590 0 R 5591 0 R] >> endobj 5528 0 obj << /Kids [10757 0 R 10758 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