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(M3.9.87025.TableNoteNumbered.1.Differential.inputs.for.these.standards.can.be.pla) 5948 0 R (M3.9.87202.XAnchorFigure.XRef.Target..Figure.169) 5949 0 R (M3.9.87217.XAnchorFigure.XRef.Target..Figure.146) 5950 0 R] >> endobj 5135 0 obj << /Limits [(M3.9.87855.Heading2.IBUFE3) (M4.9.14115.NumberedCont.12.Option.for.multiple.updates.Repeat.step10.step11.and.step11.as.needed)] /Names [(M3.9.87855.Heading2.IBUFE3) 5823 0 R (M3.9.88533.XAnchorFigure.XRef.Target..Figure.173) 5824 0 R (M3.9.89123.XAnchorFigure.XRef.Target..Figure.116) 5825 0 R (M3.9.89456.Heading1.New.Features) 5826 0 R (M3.9.89725.TableNoteNumbered.1.The.bidirectional.buffers.column.describes.the.IO.standards.u) 5827 0 R (M3.9.89853.Heading2.LVDS.and.LVDS25.Low.Voltage.Differential.Signaling) 5828 0 R (M3.9.89939.XAnchorFigure.XRef.Target..Figure.110) 5829 0 R (M3.9.90471.FigureTitle.Figure.122.InputOutput.Buffer.DCI.Enable.Primitive.IOBUFDC) 5830 0 R (M3.9.90647.Heading2.IBUFDSDPHY) 5831 0 R (M3.9.90819.TableNoteNumbered.1.ENABLEPREEMPHASIS.must.be.set.to.TRUE) 5832 0 R (M3.9.90838.Heading2.Output.Slew.Rate.Attributes) 5833 0 R (M3.9.91277.FigureTitle.Figure.140.Differential.Bidirectional.Buffer.With.Input.Buffe) 5834 0 R (M3.9.91421.FigureTitle.Figure.15.Basic.SingleEnded.HighRange.IOB.Diagram) 5835 0 R (M3.9.91531.XAnchorFigure.XRef.Target..Figure.172) 5836 0 R (M3.9.92220.XAnchorFigure.XRef.Target..Figure.125) 5837 0 R (M3.9.92278.Heading2.Transmitter.PreEmphasis) 5838 0 R (M3.9.92855.Heading2.SplitTermination.DCI.Thevenin.Equivalent.Termina) 5839 0 R (M3.9.93080.XAnchorFigure.XRef.Target..Figure.123) 5840 0 R (M3.9.93174.XAnchorFigure.XRef.Target..Figure.124) 5841 0 R (M3.9.93384.XAnchorFigure.XRef.Target..Figure.181) 5842 0 R (M3.9.93583.XAnchorFigure.XRef.Target..Figure.158) 5843 0 R (M3.9.93769.XAnchorFigure.XRef.Target..Figure.118) 5844 0 R (M3.9.94243.TableTitle.Table.15) 5845 0 R (M3.9.94309.TableNoteNumberedCont.4.INTERMSingle.and.OUTTERMDRIVER.for.HP.IO.ba) 5846 0 R (M3.9.94917.TableNoteNumberedCont.3) 5847 0 R (M3.9.95281.TableNoteNumberedCont.5.If.the.VCCO.voltage.exceeds.285V.the.outputs.are.3stated) 5848 0 R (M3.9.95401.Heading3.Receiver.Termination) 5849 0 R (M3.9.95737.Heading2.IOBUFDSDCIEN) 5850 0 R (M3.9.96199.Heading2.7Series.FPGA.IO.Resource.VHDLVerilog.Examples) 5851 0 R (M3.9.96376.XAnchorFigure.XRef.Target..Figure.117) 5852 0 R (M3.9.96928.Heading2.DQSBIAS) 5853 0 R (M3.9.96949.XAnchorFigure.XRef.Target..Figure.140) 5854 0 R (M3.9.97013.TableTitle.Table.14.All.DCI.IO.Standards.Supporting.SingleTermination.DCI) 5855 0 R (M3.9.97059.TableNoteNumberedCont.3) 5856 0 R (M3.9.97931.TableTitle.Table.148.Available.IO.Bank.Type) 5857 0 R (M3.9.98176.TableTitle.Table.152.Allowed.Combinations.of.OUTPUTIMPEDANCE.and.PREEMPHASIS) 5858 0 R (M3.9.98202.XAnchorFigure.XRef.Target..Figure.180) 5859 0 R (M3.9.98258.FigureTitle.Figure.159.Example.Circuit.for.ACCoupled.and.DCBiased.Diffe) 5860 0 R (M3.9.98304.TableNoteNumberedCont.3) 5861 0 R (M3.9.98560.XAnchorFigure.XRef.Target..Figure.128) 5862 0 R (M3.9.98653.TableNoteNumberedCont.2.ODTRTTNONE.is.not.a.valid.setting.for.DCI.IO) 5863 0 R (M3.9.98936.XAnchorFigure.XRef.Target..Figure.143) 5864 0 R (M3.9.99335.Heading2.IOBUFDSDIFFOUTINTERMDISABLE) 5865 0 R (M3.9.99439.TableTitle.Table.14.Allowed.Values.for.the.DRIVE.Attribute) 5866 0 R (M3.9.99640.Heading2.Using.DCI.with.the.Multifunction.Configuration.Pi) 5867 0 R (M3.9.99893.Body.The.guidelines.when.using.DCI.cascading.are.as.follows) 5868 0 R (M3.9.99930.Heading2.Output.Drive.Strength.Attributes) 5869 0 R (M3.9.DCIIO.banking.rules) 5870 0 R (M3.9.IOSTANDARD) 5871 0 R (M3.9.SelectIOlocation.constraints) 5872 0 R (M4.9.10559.XAnchorFigure.XRef.Target..Figure.241) 5873 0 R (M4.9.10771.NumberedCont.5.Continue.with.the.following.postreset.sequence) 5874 0 R (M4.9.11068.ZCaution.CAUTION.When.no.precautions.are.taken.in.the.application.d) 5875 0 R (M4.9.11320.EqnNum.Equation24.CNTVALUEIN.ODELAY..wanted.delay..single.tap) 5876 0 R (M4.9.11606.NumberedCont.2.Wait.a.minimum.of.10CLK.cycles) 5877 0 R (M4.9.11738.XAnchorFigure.XRef.Target..Figure.243) 5878 0 R (M4.9.11791.Heading4.UPDATEMODE.Attribute) 5879 0 R (M4.9.11799.Heading2.TXBITSLICETRI) 5880 0 R (M4.9.12382.XAnchorFigure.XRef.Target..Figure.261) 5881 0 R (M4.9.12390.Body.If.DELAYTYPE.is.VARLOAD.and.DELAYFORMAT.is.TIME.the) 5882 0 R (M4.9.12714.XAnchorFigure.XRef.Target..Figure.225) 5883 0 R (M4.9.13092.TableTitle.Table.29.ISERDESE3.Attributes) 5884 0 R (M4.9.13723.ZTip.TIP.A.used.BITSLICE0.within.a.nibble.or.a.combinatori) 5885 0 R (M4.9.14115.NumberedCont.12.Option.for.multiple.updates.Repeat.step10.step11.and.step11.as.needed) 5886 0 R] >> endobj 5136 0 obj << /Limits [(M4.9.14141.TableTitle.Table.240.Register.Bit.Description.NIBBLECTRL1) (M4.9.34976.EqnNum.Equation214.T..1316T)] /Names [(M4.9.14141.TableTitle.Table.240.Register.Bit.Description.NIBBLECTRL1) 5759 0 R (M4.9.14496.XAnchorFigure.XRef.Target..Figure.213) 5760 0 R (M4.9.14618.TableTitle.Table.21.IDELAYE3.Port.List.and.Definitions) 5761 0 R (M4.9.15579.XAnchorFigure.XRef.Target..Figure.249) 5762 0 R (M4.9.15634.XAnchorFigure.XRef.Target..Figure.218) 5763 0 R (M4.9.16124.EqnNum.Equation215..For.4bit.2T..18T) 5764 0 R (M4.9.16228.Heading4.CASCADE.Attribute) 5765 0 R (M4.9.17345.EqnNum.Equation27.DDR.PLLMMCM.clock..2..3125MHz) 5766 0 R (M4.9.17617.NumberedCont.7.xxPut.the.new.delay.line.value.on.the.CNTVALUEIN80.bus) 5767 0 R (M4.9.17642.TableTitle.Table.228.TXBITSLICETRI.Attributes) 5768 0 R (M4.9.17903.XAnchorFigure.XRef.Target..Figure.237) 5769 0 R (M4.9.18251.CellBodyMid.REFCLK) 5770 0 R (M4.9.18489.XAnchorFigure.XRef.Target..Figure.232) 5771 0 R (M4.9.18867.XAnchorFigure.XRef.Target..Figure.231) 5772 0 R (M4.9.18904.EqnNum.Equation212.INPUTDELAYCNT..OUTPUTDELAYCNT..AlignDelay.) 5773 0 R (M4.9.19274.TableNoteNumbered.1.When.in.TIME.mode.calibration.will.affect.the.ava) 5774 0 R (M4.9.19693.Heading2.IDDRE1) 5775 0 R (M4.9.19702.Heading4.DELAYVALUE.Attribute) 5776 0 R (M4.9.20687.NumberedCont.4.Read.CNTVALUEOUT80.and.load.the.value.into.a.re) 5777 0 R (M4.9.20726.Heading2.TXBITSLICE) 5778 0 R (M4.9.21227.XAnchorFigure.XRef.Target..Figure.218) 5779 0 R (M4.9.21246.XAnchorFigure.XRef.Target..Figure.226) 5780 0 R (M4.9.21590.XAnchorFigure.XRef.Target..Figure.244) 5781 0 R (M4.9.21671.NumberedCont.3.xxxUse.the.CE.and.INC.ports.to.increment.or.decrement.t) 5782 0 R (M4.9.21888.TableNoteNumbered.1.Value.depends.upon.the.UPDATEMODE.attribute.See) 5783 0 R (M4.9.22166.XAnchorFigure.XRef.Target..Figure.236) 5784 0 R (M4.9.22290.NumberedCont.2.Make.ENVTC.Low.to.modify.the.delay.line) 5785 0 R (M4.9.22551.Heading3.TXBITSLICETRI.Function) 5786 0 R (M4.9.22963.NumberedCont.4.xxxRead.CNTVALUEOUT80.and.load.the.value.into.a.regi) 5787 0 R (M4.9.23472.XAnchorFigure.XRef.Target..Figure.237) 5788 0 R (M4.9.25403.FigureTitle.Figure.213.ISERDES.FIFO.Latency.with.DATAWIDTH..4) 5789 0 R (M4.9.25427.Heading4.Step.3.Continuous.VT.Tracking) 5790 0 R (M4.9.25813.XAnchorFigure.XRef.Target..Figure.258) 5791 0 R (M4.9.25866.XAnchorFigure.XRef.Target..Figure.228) 5792 0 R (M4.9.25905.NumberedSubCont.d.Release.the.reset.for.IDELAYCTRL) 5793 0 R (M4.9.26559.TableTitle.Table.26.ISERDESE3.Output.Connections.in.SDR.and.DDR.Modes) 5794 0 R (M4.9.26623.XAnchorFigure.XRef.Target..Figure.215) 5795 0 R (M4.9.26720.TableTitle.Table.243.NEED.TITLE.) 5796 0 R (M4.9.27105.NumberedSub.a.Increment.or.decrement.the.current.tap.position.O) 5797 0 R (M4.9.27118.EqnNum.Equation211.DELAYVALUE..OUTPUTDELAYCNT..single.tap.psta) 5798 0 R (M4.9.27374.XAnchorFigure.XRef.Target..Figure.17) 5799 0 R (M4.9.28443.XAnchorFigure.XRef.Target..Figure.24) 5800 0 R (M4.9.28959.Heading3.OPPOSITEEDGE.Mode) 5801 0 R (M4.9.29339.Heading4.FIXED.Mode) 5802 0 R (M4.9.29451.NumberedSub.a.Calculate.the.difference.DifVal.between.NewVAl) 5803 0 R (M4.9.30272.Heading1.Register.Interface.Unit) 5804 0 R (M4.9.30419.Heading3.DELAYTYPE.Attribute) 5805 0 R (M4.9.30758.EqnNum.Equation22.odd.channel.DELAYVALUE..n.taps.) 5806 0 R (M4.9.31204.TableTitle.Table.26.IDDR.Port.Signals) 5807 0 R (M4.9.31444.Heading2.OSERDESE3) 5808 0 R (M4.9.31938.NumberedCont.2.Read.CNTVALUEOUT80.and.load.the.value.into.a.re) 5809 0 R (M4.9.31938.XAnchorFigure.XRef.Target..Figure.260) 5810 0 R (M4.9.31996.FigureTitle.Figure.230.Variable.Mode.UPDATEMODEASYNC) 5811 0 R (M4.9.32116.Heading3.Native.Output.Delay.Type.Usage) 5812 0 R (M4.9.32339.XAnchorFigure.XRef.Target..Figure.23) 5813 0 R (M4.9.33203.NumberedCont.5.Assert.the.ENVTC.pin) 5814 0 R (M4.9.33942.Heading3.Delay.Modes) 5815 0 R (M4.9.34190.Heading4.Register.Definitions.and.Addresses) 5816 0 R (M4.9.34195.NumberedCont.6.Wait.a.minimum.of.10.clock.cycles) 5817 0 R (M4.9.34286.FigureTitle.Figure.238) 5818 0 R (M4.9.34528.CellHeading.SerDes.Output.Data.Bits.to.Use) 5819 0 R (M4.9.34531.XAnchorFigure.XRef.Target..Figure.231) 5820 0 R (M4.9.34864.XAnchorFigure.XRef.Target..Figure.213) 5821 0 R (M4.9.34976.EqnNum.Equation214.T..1316T) 5822 0 R] >> endobj 5137 0 obj << /Limits [(M4.9.35054.XAnchorFigure.XRef.Target..Figure.25) (M4.9.52390.NumberedCont.2.Wait.a.minimum.of.10.CLK.cycles)] /Names [(M4.9.35054.XAnchorFigure.XRef.Target..Figure.25) 5695 0 R (M4.9.35081.Heading1.Bidirectional.Operation.Using.Native.Mode) 5696 0 R (M4.9.35104.Heading4.VARIABLE.Mode) 5697 0 R (M4.9.35143.XAnchorFigure.XRef.Target..Figure.254) 5698 0 R (M4.9.35281.Heading4.VARLOAD.Mode) 5699 0 R (M4.9.35520.TableNoteNumbered.1.When.in.TIME.mode.calibration.will.affect.the.ava) 5700 0 R (M4.9.35705.XAnchorFigure.XRef.Target..Figure.245) 5701 0 R (M4.9.36089.Heading3.Release.Reset) 5702 0 R (M4.9.36730.NumberedCont.7.Wait.for.at.least.10.clock.cycles) 5703 0 R (M4.9.37105.Heading4.DELAYFORMAT.Attribute) 5704 0 R (M4.9.38433.XAnchorFigure.XRef.Target..Figure.252) 5705 0 R (M4.9.38741.TableNoteNumbered.1.IO.RX.Connections.between.the.RXBITSLICE.side.of.the.RXTX) 5706 0 R (M4.9.39082.TableTitle.Table.111.ODELAYE3.Attributes) 5707 0 R (M4.9.39373.TableTitle.Table.231.Attributes.for.InterByte.Clocking.Example) 5708 0 R (M4.9.39449.CellBody.REFCLKFREQUENCY) 5709 0 R (M4.9.39575.XAnchorFigure.XRef.Target..Figure.233) 5710 0 R (M4.9.39676.XAnchorFigure.XRef.Target..Figure.240) 5711 0 R (M4.9.40753.Heading4.FIXED.Mode) 5712 0 R (M4.9.41640.XAnchorFigure.XRef.Target..Figure.264) 5713 0 R (M4.9.41841.TableNoteNumbered.1.For.memory.designs.using.RLDLYRNK.the.RIU.clock) 5714 0 R (M4.9.42387.EqnNum.Equation29.odd.channel.DELAYVALUE..n.taps.) 5715 0 R (M4.9.42573.Heading3.SAMEEDGE.Mode) 5716 0 R (M4.9.42835.XAnchorFigure.XRef.Target..Figure.239) 5717 0 R (M4.9.42873.TableTitle.Table.232.Enabling.InterNibble.Clocking) 5718 0 R (M4.9.42892.XAnchorFigure.XRef.Target..Figure.247) 5719 0 R (M4.9.43755.NumberedCont.6.Calculate.the.new.delay.value.to.be.written.in.the) 5720 0 R (M4.9.44105.EqnNum.Equation210.CNTVALUEIN..wanted.delay..singl) 5721 0 R (M4.9.44187.NumberedCont.5.xxxPut.the.new.delay.line.value.on.the.CNTVALUEIN80) 5722 0 R (M4.9.44304.TableTitle.Table.246.Need.a.title) 5723 0 R (M4.9.44388.EqnNum.Equation25.forwarded.clock..2..3125MHz) 5724 0 R (M4.9.44590.TableTitle.Table.248.Register.Bit.Description.ODELAYxx) 5725 0 R (M4.9.44759.FigureTitle.Figure.24.IDELAYCTRL) 5726 0 R (M4.9.44852.XAnchorFigure.XRef.Target..Figure.261) 5727 0 R (M4.9.44913.FigureTitle.Figure.212.ISERDES.FIFO.Latency.with.DATAWIDTH..8) 5728 0 R (M4.9.44926.TableNoteNumbered.1.When.in.TIME.mode.calibration.affects.the.availab) 5729 0 R (M4.9.44969.TableTitle.Table.259.Register.Bit.Description.DBGWRSTATUS) 5730 0 R (M4.9.45319.Heading2.Component.Mode.Reset.Sequence) 5731 0 R (M4.9.45476.NumberedCont.2.The.FIFOEMPTY.status.signal.is.High.showing.that) 5732 0 R (M4.9.45732.NumberedSub.a.Increment.or.decrement.the.current.tap.position.O) 5733 0 R (M4.9.45923.Heading4.DELAYSRC.Attribute) 5734 0 R (M4.9.45952.Heading4.DELAYFORMAT.Attribute) 5735 0 R (M4.9.46294.ZTip.TIP.Using.the.OUTPUTPHASE90.attribute.allows.the.ser) 5736 0 R (M4.9.47016.TableTitle.Table.28.OSERDESE3.Output.Connections.in.SDR.and.DDR.Modes) 5737 0 R (M4.9.47338.XAnchorFigure.XRef.Target..Figure.256) 5738 0 R (M4.9.47363.TableTitle.Table.257.Register.Bit.Description.DBGRDSTATUS) 5739 0 R (M4.9.47480.TableNoteNumbered.1.Only.valid.port.combinations.are.provided.in.the.t) 5740 0 R (M4.9.48257.XAnchorFigure.XRef.Target..Figure.236) 5741 0 R (M4.9.48503.Heading4.CASCADE.Attribute) 5742 0 R (M4.9.48585.EqnNum.Equation213.CNTVALUEIN..wanted.delay..single.tap..AlignD) 5743 0 R (M4.9.49356.CellBody.DELAYVALUE) 5744 0 R (M4.9.49369.TableTitle.Table.235.RIU.Ports) 5745 0 R (M4.9.50133.TableNoteNumbered.1.IO.RX.Connections.between.the.RXBITSLICE.side.of.the.RXTX) 5746 0 R (M4.9.50254.XAnchorFigure.XRef.Target..Figure.251) 5747 0 R (M4.9.50463.CellBodyMid.REFCLKFREQUENCY) 5748 0 R (M4.9.50540.TableTitle.Table.236.Register.Bit.Description.NIBBLECRTL0) 5749 0 R (M4.9.50677.TableTitle.Table.220.RXTXBITSLICE.Ports) 5750 0 R (M4.9.50685.Heading4.VARLOAD.Mode) 5751 0 R (M4.9.50837.XAnchorFigure.XRef.Target..Figure.259) 5752 0 R (M4.9.50844.XAnchorFigure.XRef.Target..Figure.250) 5753 0 R (M4.9.51504.Heading3.FIFO) 5754 0 R (M4.9.51736.EqnNum.Equation216.T..1416T) 5755 0 R (M4.9.51795.NumberedCont.4.Calculate.the.new.delay.value.in.taps.to.be.writ) 5756 0 R (M4.9.52142.XAnchorFigure.XRef.Target..Figure.228) 5757 0 R (M4.9.52390.NumberedCont.2.Wait.a.minimum.of.10.CLK.cycles) 5758 0 R] >> endobj 5138 0 obj << /Limits [(M4.9.53383.XAnchorFigure.XRef.Target..Figure.211) (M4.9.70553.XAnchorFigure.XRef.Target..Figure.237)] /Names [(M4.9.53383.XAnchorFigure.XRef.Target..Figure.211) 5631 0 R (M4.9.53980.XAnchorFigure.XRef.Target..Figure.231) 5632 0 R (M4.9.54105.NumberedCont.2.Make.ENVTC.low.to.modify.the.delay.line) 5633 0 R (M4.9.54698.TableTitle.Table.252.Register.Bit.Description.PQTRRATIO.NQTRRATIO) 5634 0 R (M4.9.55135.NumberedCont.9.Option.for.multiple.updates.Wait.5.clock.cycles) 5635 0 R (M4.9.55442.TableTitle.Table.244.Register.Bit.Description.PQTR) 5636 0 R (M4.9.55613.TableTitle.Table.223.RXBITSLICE.Attributes) 5637 0 R (M4.9.55669.NumberedCont.4.Wait.a.minimum.of.5.clock.cycles) 5638 0 R (M4.9.55781.NumberedCont.2.Read.CNTVALUEOUT80.and.load.the.value.into.a.re) 5639 0 R (M4.9.56612.XAnchorFigure.XRef.Target..Figure.212) 5640 0 R (M4.9.56838.TableTitle.Table.28.ISERDESE3.Port.List) 5641 0 R (M4.9.56854.CellBodyMid.ISRSTINVERTED) 5642 0 R (M4.9.56960.Heading4.VARLOAD.Mode) 5643 0 R (M4.9.57009.Heading2.Output.Delay) 5644 0 R (M4.9.57491.EqnNum.Equation216.CNTVALUEIN.TXBITSLICE..wanted.delaysingle.ta) 5645 0 R (M4.9.57596.XAnchorFigure.XRef.Target..Figure.211) 5646 0 R (M4.9.57798.FigureTitle.Figure.218) 5647 0 R (M4.9.58638.XAnchorFigure.XRef.Target..Figure.228) 5648 0 R (M4.9.59150.TableTitle.Table.223.TXBITSLICE.Attributes) 5649 0 R (M4.9.59325.Heading3.SAMEEDGEPIPELINED.Mode) 5650 0 R (M4.9.59355.ZCaution.CAUTION.IDELAYE3.ISERDESE3.and.IDDRE1.lines.used.and.positioned.at.IO) 5651 0 R (M4.9.60580.TableTitle.Table.210.OSERDESE3.Attributes) 5652 0 R (M4.9.60998.Heading4.Release.Reset) 5653 0 R (M4.9.61017.FigureTitle.Figure.29.ODDR.with.Internal.Logic.FlipFlop.3State) 5654 0 R (M4.9.61210.Heading4.FIXED.Mode) 5655 0 R (M4.9.61284.NumberedCont.5.5.Wait.for.at.least.10.clock.cycles) 5656 0 R (M4.9.61317.TableNoteNumbered.1.xxWhen.in.TIME.mode.calibration.affects.the.avail) 5657 0 R (M4.9.61369.EqnNum.Equation28.TotalValue..DlyAlign..n.taps) 5658 0 R (M4.9.61433.Heading1.Component.Mode) 5659 0 R (M4.9.61452.NumberedCont.2.Make.ENVTC.Low.to.modify.the.delay.line) 5660 0 R (M4.9.61581.XAnchorFigure.XRef.Target..Figure.217) 5661 0 R (M4.9.61964.ZTip.TIP.When.using.an.IBUFDSDIFFOUT.both.RXTXBITSLICEs) 5662 0 R (M4.9.62220.Heading2.RXBITSLICE) 5663 0 R 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