############################################################################ ## DISCLAIMER: ## XILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, ## SCHEMATIC, AND/OR SPECIFICATION (THE "DOCUMENTATION")TO YOU SOLELY ## FOR USE IN THE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX ## HARDWARE DEVICES. YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, ## DOWNLOAD, DISPLAY, POST, OR TRANSMIT THE DOCUMENTATION IN ANY FORM ## OR BY ANY MEANS INCLUDING, BUT NOT LIMITED TO, ELECTRONIC, ## MECHANICAL, PHOTOCOPYING, RECORDING, OR OTHERWISE, WITHOUT THE ## PRIOR WRITTEN CONSENT OF XILINX. XILINX EXPRESSLY DISCLAIMS ANY ## LIABILITY ARISING OUT OF YOUR USE OF THE DOCUMENTATION. ## XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION, TO CHANGE THE ## DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMES NO ## OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION, ## OR TO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLY ## DISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT OR ## ASSISTANCETHAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THE ## DOCUMENTATION. ## THE DOCUMENTATION IS DISCLOSED TO YOU "AS-IS" WITH NO WARRANTY OF ## ANY OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINXBE LIABLE FOR ANY ## MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR ## NONINFRINGEMENT STATUTORY, REGARDING THEDOCUMENTATION, INCLUDING ## ANY WARRANTIES OF KIND. ## XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR THE ## DOCUMENTATION. INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING ## FROM YOUR USE OF CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR ## INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ## ARISING FROM YOUR USE OF THE DOCUMENTATION. ## ## ################################################################################################################################################################## ## U45N - Master XDC ## Revision 1.00 - Initial Release for U45N ################################################################################################################################################################## ## Key Notes: ## 1) PCIe Clocks Support x16 and x8 Bifurcation with both synchronous or asynchronous operation ## 2) Board will operate with PCIe edge power as well as with 2x3 PCIe AUX power connected. ## 3) NA ################################################################################################################################################################## ## ## Clock Trees ## ## ## 1) Si5394J- SiLabs Si5394J-A12400-GM Programmable Clock Generator (Re-programming I2C access ONLY possible via Satellite Controller) ## | ## | ## |-> OUT0 CLK_4_HCSL_100_P/CLK_4_HCSL_100_N 100.000Mhz - Onboard ARM SD2 PLL REFCLK ## ## |-> OUT1 SI53306-B-GM-1:4 Low Jitter Clock Buffer ## | | ## | |-> OUT0 CLK_0_HCSL_161_P/CLK_0_HCSL_161_N 161.1328125Mhz - onboard QSFP#1 GTY Ref Clock ## | | PINS: MGTREFCLK0P_231_P9/MGTREFCLK0N_231_P8 ## | | ## | |-> OUT1 CLK_1_HCSL_161_P/CLK_1_HCSL_161_N 161.1328125Mhz - onboard QSFP#0 GTM Ref Clock Bank 233 ## | | PINS: MGTREFCLKP_233_J10/MGTREFCLKN_233_J9 ## | | ## | |-> OUT2 CLK_2_HCSL_161_P/CLK_2_HCSL_161_N 161.1328125Mhz - onboard QSFP#0 GTM Ref Clock Bank 234 ## | | PINS: MGTREFCLKP_234_G10/MGTREFCLKN_234_G9 ## | | ## | |-> OUT3 CLK_3_HCSL_161_P/CLK_3_HCSL_161_N 161.1328125Mhz - onboard ARM SOC SD1 REFCLK ## ## |-> OUT2 SI53306-B-GM-1:4 Low Jitter Clock Buffer ## | | ## | |-> OUT0 CLK_0_HCSL_100_P/CLK_0_HCSL_100_N 100Mhz - onboard ARM SOC DIFF_SYSCLK ## | | ## | |-> OUT1 CLK_1_HCSL_100_P/CLK_1_HCSL_161_N 100Mhz - onboard PCIe Ref Clock Bank 225 ## | | PINS: MGTREFCLK1P_225_AK8/MGTREFCLK1N_225_AK7 ## | | ## | |-> OUT2 CLK_2_HCSL_100_P/CLK_2_HCSL_100_N 100Mhz - onboard PCIe Ref Clock Bank 227 ## | | PINS: MGTREFCLK1P_227_AE10/MGTREFCLK1N_227_AE9 ## | | ## | |-> OUT3 CLK_3_HCSL_100_P/CLK_3_HCSL_100_N 100Mhz - onboard ARM SOC to FPGA interface Ref Clock Bank 228 ## | | PINS: MGTREFCLK0P_228_AC10/MGTREFCLK0N_228_AC9 ## ## |-> OUT3 SI53306-B-GM-1:4 Low Jitter Clock Buffer ## | | ## | |-> OUT0 DDR4_C0_SYSCLK_P/DDR4_C0_SYSCLK_N 300.000Mhz - onboard DDR4 Clock ## | | PINS: IO_L13P_T2L_N0_GC_QBC_66_AN27/IO_L13N_T2L_N1_GC_QBC_66_AN28 ## | | ## | |-> OUT1 CLK_0_LVDS_300_P/CLK_0_LVDS_300_N 300.000Mhz - onboard System Clock ## | | PINS: IO_L11P_T1U_N8_GC_A10_D26_65_AK23/IO_L11N_T1U_N9_GC_A11_D27_65_AL23 ## | | ## | |-> OUT2 DDR4_C1_SYSCLK_P/DDR4_C1_SYSCLK_N 300.000Mhz - onboard DDR4 Clock ## | | PINS: IO_L13P_T2L_N0_GC_QBC_72_H34/IO_L13N_T2L_N1_GC_QBC_72_H35 ## | | ## | |-> OUT3 Not Used ## ## ## 2) PCIE Fingers PEX_REFCLK_P/PEX_REFCLK_N 100.000Mhz ## |-> Si53102-A3-GMR --> OUT1 PCIE_REFCLK0_P/PCIE_REFCLK0_N 100.000Mhz - PCIe REFCLK0 for x16 and Bifurcated x8 Lanes 8-15 synchronous Clocking ## | PINS: MGTREFCLK0P_225_AL10/MGTREFCLK0N_225_AL9 ## | ## |-> OUT2 PCIE_REFCLK1_P/PCIE_REFCLK1_N 100.000Mhz - PCIe REFCLK0 for Bifurcated x8 Lanes 0-7 synchronous Clocking ## PINS: MGTREFCLK0P_227_AF8/MGTREFCLK0N_227_AF7 ## ## ## 3) SiTime SiT8009BI-73-18E-125.000000E 125MHz ## |->OUT CLK_EMCCLK_125M_BANK65 - 125.00MHz EMCCLK ## | PINS: IO_L24P_T3U_N10_EMCCLK_65_AH17 ## ## ## 4) SiTime SiT8008BI-73-18E-100.000000E 100MHz ## |->OUT CLK_100M_ARM - 100.00MHz ARM SOC Ref CLK ## ################################################################################################################################################################## ## ## Bitstream Configuration ## #################################################################################################################################################################### ## set_property CONFIG_VOLTAGE 1.8 [current_design] set_property CFGBVS GND [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 72.9 [current_design] set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] ## ################################################################################################################################################################## ## ## Power Constraint to warn User if Design will possibly be over cards power limit, this assume the 2x4 PCIe AUX power is connectd to the board. ## ################################################################################################################################################################## set_operating_conditions -design_power_budget 160 ################################################################################################################################################################## ## ## Sys Ref Clock & EMCCLK clock ## ################################################################################################################################################################## set_property PACKAGE_PIN AL23 [get_ports "sysclk_300_n"] ;# Bank 65 VCCO - 1V8 - IO_L11N_T1U_N9_GC_A11_D27_65 set_property IOSTANDARD LVDS [get_ports "sysclk_300_n"] ;# Bank 65 VCCO - 1V8 - IO_L11N_T1U_N9_GC_A11_D27_65 set_property PACKAGE_PIN AK23 [get_ports "sysclk_300_p"] ;# Bank 65 VCCO - 1V8 - IO_L11P_T1U_N8_GC_A10_D26_65 set_property IOSTANDARD LVDS [get_ports "sysclk_300_p"] ;# Bank 65 VCCO - 1V8 - IO_L11P_T1U_N8_GC_A10_D26_65 set_property PACKAGE_PIN AH17 [get_ports "CLK_EMCCLK_125M_BANK65"] ;# Bank 65 VCCO - 1V8 - IO_L24P_T3U_N10_EMCCLK_65 set_property IOSTANDARD LVCMOS18 [get_ports "CLK_EMCCLK_125M_BANK65"] ;# Bank 65 VCCO - 1V8 - IO_L24P_T3U_N10_EMCCLK_65 create_clock -period 8.000 -name emcclk [get_ports "CLK_EMCCLK_125M_BANK65"] create_clock -period 3.333 -name sysclk [get_ports "CLK_0_LVDS_300_P"] ################################################################################################################################################################## ## ## LVDS Input SYSTEM CLOCKS for Memory Interfaces (1.2V banks ) ## external BIAS on AC coupled LVDS clock inputs is DNP so DQS_BIAS constraint is added to recenter LVDS signal on 1.2V IO standard. ## ################################################################################################################################################################## set_property PACKAGE_PIN AN28 [get_ports "c0_sys_clk_n"] ;# Bank 66 VCCO - -Net DDR4_C0_SYSCLK_N - IO_L13N_T2L_N1_GC_QBC_66 set_property IOSTANDARD LVDS [get_ports "c0_sys_clk_n"] ;# Bank 66 VCCO - -Net DDR4_C0_SYSCLK_N - IO_L13N_T2L_N1_GC_QBC_66 set_property PACKAGE_PIN AN27 [get_ports "c0_sys_clk_p"] ;# Bank 66 VCCO - -Net DDR4_C0_SYSCLK_P - IO_L13P_T2L_N0_GC_QBC_66 set_property IOSTANDARD LVDS [get_ports "c0_sys_clk_p"] ;# Bank 66 VCCO - -Net DDR4_C0_SYSCLK_P - IO_L13P_T2L_N0_GC_QBC_66 set_property DQS_BIAS TRUE [get_ports "c0_sys_clk_p"] ;# Bank 66 VCCO - -Net DDR4_C0_SYSCLK_P - IO_L13P_T2L_N0_GC_QBC_66 set_property PACKAGE_PIN H35 [get_ports "c1_sys_clk_n"] ;# Bank 72 VCCO - -Net DDR4_C1_SYSCLK_N - IO_L13N_T2L_N1_GC_QBC_72 set_property IOSTANDARD LVDS [get_ports "c1_sys_clk_n"] ;# Bank 72 VCCO - -Net DDR4_C1_SYSCLK_N - IO_L13N_T2L_N1_GC_QBC_72 set_property PACKAGE_PIN H34 [get_ports "c1_sys_clk_p"] ;# Bank 72 VCCO - -Net DDR4_C1_SYSCLK_P - IO_L13P_T2L_N0_GC_QBC_72 set_property IOSTANDARD LVDS [get_ports "c1_sys_clk_p"] ;# Bank 72 VCCO - -Net DDR4_C1_SYSCLK_P - IO_L13P_T2L_N0_GC_QBC_72 set_property DQS_BIAS TRUE [get_ports "c1_sys_clk_p"] ;# Bank 72 VCCO - -Net DDR4_C1_SYSCLK_P - IO_L13P_T2L_N0_GC_QBC_72 create_clock -period 3.333 -name c0sysclk [get_ports "c0_sys_clk_p"] create_clock -period 3.333 -name c1sysclk [get_ports "c1_sys_clk_p"] ################################################################################################################################################################## ## ## Input Clocks for Gen3 x16 or Dual x8 Bifurcation on Lane 8-15 ## PCIe 100Mhz Host clock ## ################################################################################################################################################################## set_property PACKAGE_PIN AL9 [get_ports "PCIE_REFCLK0_N"] ;# Bank 225 - MGTREFCLK0N_225 set_property PACKAGE_PIN AL10 [get_ports "PCIE_REFCLK0_P"] ;# Bank 225 - MGTREFCLK0P_225 set_property PACKAGE_PIN AF7 [get_ports "PCIE_REFCLK1_N"] ;# Bank 227 - MGTREFCLK0N_227 set_property PACKAGE_PIN AF8 [get_ports "PCIE_REFCLK1_P"] ;# Bank 227 - MGTREFCLK0P_227 create_clock -period 10.000 -name pcierefclk0 [get_ports "PCIE_REFCLK0_P"] create_clock -period 10.000 -name pcierefclk1 [get_ports "PCIE_REFCLK1_P"] ################################################################################################################################################################## ## ## onboard Input Sysclock for PCIe/QSFP ## ################################################################################################################################################################## set_property PACKAGE_PIN AK7 [get_ports "CLK_1_HCSL_100_N"] ;# Bank 225 - MGTREFCLK1N_225 set_property PACKAGE_PIN AK8 [get_ports "CLK_1_HCSL_100_P"] ;# Bank 225 - MGTREFCLK1P_225 set_property PACKAGE_PIN AE9 [get_ports "CLK_2_HCSL_100_N"] ;# Bank 227 - MGTREFCLK1N_227 set_property PACKAGE_PIN AE10 [get_ports "CLK_2_HCSL_100_P"] ;# Bank 227 - MGTREFCLK1P_227 set_property PACKAGE_PIN AC9 [get_ports "CLK_3_HCSL_100_N"] ;# Bank 228 - MGTREFCLK0N_228 set_property PACKAGE_PIN AC10 [get_ports "CLK_3_HCSL_100_P"] ;# Bank 228 - MGTREFCLK0P_228 set_property PACKAGE_PIN P8 [get_ports "CLK_0_HCSL_161_N"] ;# Bank 231 - MGTREFCLK0N_231 set_property PACKAGE_PIN P9 [get_ports "CLK_0_HCSL_161_P"] ;# Bank 231 - MGTREFCLK0P_231 set_property PACKAGE_PIN J9 [get_ports "CLK_1_HCSL_161_N"] ;# Bank 233 - MGTREFCLKN_233 set_property PACKAGE_PIN J10 [get_ports "CLK_1_HCSL_161_P"] ;# Bank 233 - MGTREFCLKP_233 set_property PACKAGE_PIN G9 [get_ports "CLK_2_HCSL_161_N"] ;# Bank 234 - MGTREFCLKN_234 set_property PACKAGE_PIN G10 [get_ports "CLK_2_HCSL_161_P"] ;# Bank 234 - MGTREFCLKP_234 create_clock -period 10.000 -name pciesysclk0 [get_ports "CLK_1_HCSL_100_P"] create_clock -period 10.000 -name pciesysclk1 [get_ports "CLK_2_HCSL_100_P"] create_clock -period 10.000 -name armsysclk [get_ports "CLK_3_HCSL_100_P"] create_clock -period 6.2070 -name qsfpclk0 [get_ports "CLK_0_HCSL_161_P"] create_clock -period 6.2070 -name qsfpclk1 [get_ports "CLK_1_HCSL_161_P"] create_clock -period 6.2070 -name qsfpclk2 [get_ports "CLK_2_HCSL_161_P"] ################################################################################################################################################################## ## ## Bank 65 FPGA to Satellite Controller CMS UART Interface (115200, No parity, 8 bits, 1 stop bit) ## FPGA_SUC_TXD Output from Satellite Controller UART to FPGA ## FPGA_SUC_RXD Output from FPGA to Satellite Controller UART ## This interface is used for the CMS command path, refer to https://www.xilinx.com/products/intellectual-property/cms-subsystem.html and Xilinx PG348 ## ################################################################################################################################################################## set_property PACKAGE_PIN AK21 [get_ports "FPGA_SUC_RXD_R"] ;# Bank 65 VCCO - 1V8 - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 set_property IOSTANDARD LVCMOS18 [get_ports "FPGA_SUC_RXD_R"] ;# Bank 65 VCCO - 1V8 - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 set_property PACKAGE_PIN AJ21 [get_ports "FPGA_SUC_TXD_R"] ;# Bank 65 VCCO - 1V8 - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 set_property IOSTANDARD LVCMOS18 [get_ports "FPGA_SUC_TXD_R"] ;# Bank 65 VCCO - 1V8 - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 ################################################################################################################################################################## ## ## Bank 65 FPGA to NXP ARM SOC UART Interface (115200, No parity, 8 bits, 1 stop bit) ## FPGA_NXP_UART_RXD_R Output from ARM SOC UART to FPGA ## FPGA_NXP_UART_TXD_R Output from FPGA to ARM SOC UART ## ################################################################################################################################################################## set_property PACKAGE_PIN AK17 [get_ports "FPGA_NXP_UART_RXD_R"] ;# Bank 65 VCCO - 1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65 set_property IOSTANDARD LVCMOS18 [get_ports "FPGA_NXP_UART_RXD_R"] ;# Bank 65 VCCO - 1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65 set_property PACKAGE_PIN AK16 [get_ports "FPGA_NXP_UART_TXD_R"] ;# Bank 65 VCCO - 1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65 set_property IOSTANDARD LVCMOS18 [get_ports "FPGA_NXP_UART_TXD_R"] ;# Bank 65 VCCO - 1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65 ################################################################################################################################################################## ## ## Bank 65 FPGA UART Interface 0/1 to DMB-01 (User selectable Baud) ## FPGA_UART1_RXD Output from DMB-02 UART to FPGA ## FPGA_UART1_TXD Output from FPGA to DMB-02 UART ## ################################################################################################################################################################## set_property PACKAGE_PIN AR24 [get_ports "FPGA_UART1_RXD"] ;# Bank 65 VCCO - 1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65 set_property IOSTANDARD LVCMOS18 [get_ports "FPGA_UART1_RXD"] ;# Bank 65 VCCO - 1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65 set_property PACKAGE_PIN AP24 [get_ports "FPGA_UART1_TXD_R"] ;# Bank 65 VCCO - 1V8 - IO_L2P_T0L_N2_FOE_B_65 set_property IOSTANDARD LVCMOS18 [get_ports "FPGA_UART1_TXD_R"] ;# Bank 65 VCCO - 1V8 - IO_L2P_T0L_N2_FOE_B_65 ################################################################################################################################################################## ## ## General purpose IO interconnects between FPGA and Satellite Controller. ## ################################################################################################################################################################## set_property PACKAGE_PIN AM17 [get_ports "SUC_FPGA_GPIO1"] ;# Bank 65 VCCO - 1V8 - IO_L20P_T3L_N2_AD1P_D08_65 set_property IOSTANDARD LVCMOS18 [get_ports "SUC_FPGA_GPIO1"] ;# Bank 65 VCCO - 1V8 - IO_L20P_T3L_N2_AD1P_D08_65 set_property PACKAGE_PIN AL18 [get_ports "SUC_FPGA_GPIO2"] ;# Bank 65 VCCO - 1V8 - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 set_property IOSTANDARD LVCMOS18 [get_ports "SUC_FPGA_GPIO2"] ;# Bank 65 VCCO - 1V8 - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 ################################################################################################################################################################## # # NIC LED Low/Open = off, High = Glow # ################################################################################################################################################################## set_property PACKAGE_PIN AM23 [get_ports "CAGE_0_ACTIVITY_LED"] ;# Bank 65 VCCO - 1V8 - IO_L5N_T0U_N9_AD14N_A23_65 set_property IOSTANDARD LVCMOS18 [get_ports "CAGE_0_ACTIVITY_LED"] ;# Bank 65 VCCO - 1V8 - IO_L5N_T0U_N9_AD14N_A23_65 set_property PACKAGE_PIN AM22 [get_ports "CAGE_0_LINK_STAT_LEDG"] ;# Bank 65 VCCO - 1V8 - IO_L5P_T0U_N8_AD14P_A22_65 set_property IOSTANDARD LVCMOS18 [get_ports "CAGE_0_LINK_STAT_LEDG"] ;# Bank 65 VCCO - 1V8 - IO_L5P_T0U_N8_AD14P_A22_65 set_property PACKAGE_PIN AN23 [get_ports "CAGE_0_LINK_STAT_LEDY"] ;# Bank 65 VCCO - 1V8 - IO_L4N_T0U_N7_DBC_AD7N_A25_65 set_property IOSTANDARD LVCMOS18 [get_ports "CAGE_0_LINK_STAT_LEDY"] ;# Bank 65 VCCO - 1V8 - IO_L4N_T0U_N7_DBC_AD7N_A25_65 set_property PACKAGE_PIN AJ25 [get_ports "CAGE_1_ACTIVITY_LED"] ;# Bank 65 VCCO - 1V8 - IO_L7N_T1L_N1_QBC_AD13N_A19_65 set_property IOSTANDARD LVCMOS18 [get_ports "CAGE_1_ACTIVITY_LED"] ;# Bank 65 VCCO - 1V8 - IO_L7N_T1L_N1_QBC_AD13N_A19_65 set_property PACKAGE_PIN AH25 [get_ports "CAGE_1_LINK_STAT_LEDG"] ;# Bank 65 VCCO - 1V8 - IO_L7P_T1L_N0_QBC_AD13P_A18_65 set_property IOSTANDARD LVCMOS18 [get_ports "CAGE_1_LINK_STAT_LEDG"] ;# Bank 65 VCCO - 1V8 - IO_L7P_T1L_N0_QBC_AD13P_A18_65 set_property PACKAGE_PIN AN24 [get_ports "CAGE_1_LINK_STAT_LEDY"] ;# Bank 65 VCCO - 1V8 - IO_T0U_N12_VRP_A28_65 set_property IOSTANDARD LVCMOS18 [get_ports "CAGE_1_LINK_STAT_LEDY"] ;# Bank 65 VCCO - 1V8 - IO_T0U_N12_VRP_A28_65 ################################################################################################################################################################## # # Card Status LED Low/Open = off, High = Glow # ################################################################################################################################################################## set_property PACKAGE_PIN AH24 [get_ports "CARD_HEART_BIT"] ;# Bank 65 VCCO - 1V8 - IO_L9P_T1L_N4_AD12P_A14_D30_65 set_property IOSTANDARD LVCMOS18 [get_ports "CARD_HEART_BIT"] ;# Bank 65 VCCO - 1V8 - IO_L9P_T1L_N4_AD12P_A14_D30_65 set_property PACKAGE_PIN AL24 [get_ports "CARD_STATUS_LED"] ;# Bank 65 VCCO - 1V8 - IO_L8N_T1L_N3_AD5N_A17_65 set_property IOSTANDARD LVCMOS18 [get_ports "CARD_STATUS_LED"] ;# Bank 65 VCCO - 1V8 - IO_L8N_T1L_N3_AD5N_A17_65 ################################################################################################################################################################## ## ## PCIE_PERST_LS_65 Active low input from PCIe Connector to FPGA to detect the Active low Reset. ## PEX_PWRBRKN_FPGA_65 Active low input from PCIe Connector Signaling PCIe card to shut down card power in Server failing condition. ## ################################################################################################################################################################## set_property PACKAGE_PIN AK18 [get_ports "PCIE_PERST_LS_65"] ;# Bank 65 VCCO - 1V8 - IO_T3U_N12_PERSTN0_65 set_property IOSTANDARD LVCMOS18 [get_ports "PCIE_PERST_LS_65"] ;# Bank 65 VCCO - 1V8 - IO_T3U_N12_PERSTN0_65 set_property PACKAGE_PIN AM20 [get_ports "PEX_PWRBRKN_FPGA_65"] ;# Bank 65 VCCO - 1V8 - IO_L17N_T2U_N9_AD10N_D15_65 set_property IOSTANDARD LVCMOS18 [get_ports "PEX_PWRBRKN_FPGA_65"] ;# Bank 65 VCCO - 1V8 - IO_L17N_T2U_N9_AD10N_D15_65 ################################################################################################################################################################## # # Clock Generator reset/Interrupt # ################################################################################################################################################################## set_property PACKAGE_PIN AH19 [get_ports "SI_INTRB_R"] ;# Bank 65 VCCO - 1V8 - IO_L15P_T2L_N4_AD11P_A02_D18_65 set_property IOSTANDARD LVCMOS18 [get_ports "SI_INTRB_R"] ;# Bank 65 VCCO - 1V8 - IO_L15P_T2L_N4_AD11P_A02_D18_65 set_property PACKAGE_PIN AJ20 [get_ports "SI_IN_LOS_R"] ;# Bank 65 VCCO - 1V8 - IO_L14N_T2L_N3_GC_A05_D21_65 set_property IOSTANDARD LVCMOS18 [get_ports "SI_IN_LOS_R"] ;# Bank 65 VCCO - 1V8 - IO_L14N_T2L_N3_GC_A05_D21_65 set_property PACKAGE_PIN AJ19 [get_ports "SI_PLL_LOCK_R"] ;# Bank 65 VCCO - 1V8 - IO_L15N_T2L_N5_AD11N_A03_D19_65 set_property IOSTANDARD LVCMOS18 [get_ports "SI_PLL_LOCK_R"] ;# Bank 65 VCCO - 1V8 - IO_L15N_T2L_N5_AD11N_A03_D19_65 set_property PACKAGE_PIN AN20 [get_ports "SI_RSTBB_R"] ;# Bank 65 VCCO - 1V8 - IO_L18N_T2U_N11_AD2N_D13_65 set_property IOSTANDARD LVCMOS18 [get_ports "SI_RSTBB_R"] ;# Bank 65 VCCO - 1V8 - IO_L18N_T2U_N11_AD2N_D13_65 ################################################################################################################################################################## # # PCIe Reset between FPGA to NXP ARM SOC # ################################################################################################################################################################## set_property PACKAGE_PIN AJ17 [get_ports "NXP_PCIE_RESETN"] ;# Bank 65 VCCO - 1V8 - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 set_property IOSTANDARD LVCMOS18 [get_ports "NXP_PCIE_RESETN"] ;# Bank 65 VCCO - 1V8 - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 ################################################################################################################################################################## # # Test Clock Output # ################################################################################################################################################################## set_property PACKAGE_PIN AT24 [get_ports "TESTCLK_OUT"] ;# Bank 65 VCCO - 1V8 - IO_L1P_T0L_N0_DBC_RS0_65 set_property IOSTANDARD LVCMOS18 [get_ports "TESTCLK_OUT"] ;# Bank 65 VCCO - 1V8 - IO_L1P_T0L_N0_DBC_RS0_65 ################################################################################################################################################################## ## ## DDR4 DRAM Controller 1, Channel 0, 72-bit Data Interface, x16 data width ## ################################################################################################################################################################## set_property PACKAGE_PIN AT30 [get_ports "c0_ddr4_adr[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_A0 - IO_L6N_T0U_N11_AD6N_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_A0 - IO_L6N_T0U_N11_AD6N_66 set_property PACKAGE_PIN AT31 [get_ports "c0_ddr4_adr[10]"] ;# Bank 66 VCCO - -Net DDR4_C0_A10 - IO_L5N_T0U_N9_AD14N_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[10]"] ;# Bank 66 VCCO - -Net DDR4_C0_A10 - IO_L5N_T0U_N9_AD14N_66 set_property PACKAGE_PIN AP26 [get_ports "c0_ddr4_adr[11]"] ;# Bank 66 VCCO - -Net DDR4_C0_A11 - IO_L12P_T1U_N10_GC_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[11]"] ;# Bank 66 VCCO - -Net DDR4_C0_A11 - IO_L12P_T1U_N10_GC_66 set_property PACKAGE_PIN AL31 [get_ports "c0_ddr4_adr[12]"] ;# Bank 66 VCCO - -Net DDR4_C0_A12 - IO_L1N_T0L_N1_DBC_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[12]"] ;# Bank 66 VCCO - -Net DDR4_C0_A12 - IO_L1N_T0L_N1_DBC_66 set_property PACKAGE_PIN AN29 [get_ports "c0_ddr4_adr[13]"] ;# Bank 66 VCCO - -Net DDR4_C0_A13 - IO_L3P_T0L_N4_AD15P_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[13]"] ;# Bank 66 VCCO - -Net DDR4_C0_A13 - IO_L3P_T0L_N4_AD15P_66 set_property PACKAGE_PIN AJ27 [get_ports "c0_ddr4_adr[1]"] ;# Bank 66 VCCO - -Net DDR4_C0_A1 - IO_L17P_T2U_N8_AD10P_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[1]"] ;# Bank 66 VCCO - -Net DDR4_C0_A1 - IO_L17P_T2U_N8_AD10P_66 set_property PACKAGE_PIN AP30 [get_ports "c0_ddr4_adr[2]"] ;# Bank 66 VCCO - -Net DDR4_C0_A2 - IO_L4N_T0U_N7_DBC_AD7N_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[2]"] ;# Bank 66 VCCO - -Net DDR4_C0_A2 - IO_L4N_T0U_N7_DBC_AD7N_66 set_property PACKAGE_PIN AM31 [get_ports "c0_ddr4_adr[3]"] ;# Bank 66 VCCO - -Net DDR4_C0_A3 - IO_L2N_T0L_N3_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[3]"] ;# Bank 66 VCCO - -Net DDR4_C0_A3 - IO_L2N_T0L_N3_66 set_property PACKAGE_PIN AM30 [get_ports "c0_ddr4_adr[4]"] ;# Bank 66 VCCO - -Net DDR4_C0_A4 - IO_L2P_T0L_N2_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[4]"] ;# Bank 66 VCCO - -Net DDR4_C0_A4 - IO_L2P_T0L_N2_66 set_property PACKAGE_PIN AP29 [get_ports "c0_ddr4_adr[5]"] ;# Bank 66 VCCO - -Net DDR4_C0_A5 - IO_L4P_T0U_N6_DBC_AD7P_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[5]"] ;# Bank 66 VCCO - -Net DDR4_C0_A5 - IO_L4P_T0U_N6_DBC_AD7P_66 set_property PACKAGE_PIN AU25 [get_ports "c0_ddr4_adr[6]"] ;# Bank 66 VCCO - -Net DDR4_C0_A6 - IO_T1U_N12_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[6]"] ;# Bank 66 VCCO - -Net DDR4_C0_A6 - IO_T1U_N12_66 set_property PACKAGE_PIN AP27 [get_ports "c0_ddr4_adr[7]"] ;# Bank 66 VCCO - -Net DDR4_C0_A7 - IO_L12N_T1U_N11_GC_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[7]"] ;# Bank 66 VCCO - -Net DDR4_C0_A7 - IO_L12N_T1U_N11_GC_66 set_property PACKAGE_PIN AR26 [get_ports "c0_ddr4_adr[8]"] ;# Bank 66 VCCO - -Net DDR4_C0_A8 - IO_L11P_T1U_N8_GC_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[8]"] ;# Bank 66 VCCO - -Net DDR4_C0_A8 - IO_L11P_T1U_N8_GC_66 set_property PACKAGE_PIN AL26 [get_ports "c0_ddr4_adr[9]"] ;# Bank 66 VCCO - -Net DDR4_C0_A9 - IO_L16N_T2U_N7_QBC_AD3N_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[9]"] ;# Bank 66 VCCO - -Net DDR4_C0_A9 - IO_L16N_T2U_N7_QBC_AD3N_66 set_property PACKAGE_PIN AN30 [get_ports "c0_ddr4_act_n"] ;# Bank 66 VCCO - -Net DDR4_C0_ACT_B - IO_L3N_T0L_N5_AD15N_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_act_n"] ;# Bank 66 VCCO - -Net DDR4_C0_ACT_B - IO_L3N_T0L_N5_AD15N_66 set_property PACKAGE_PIN AK26 [get_ports "c0_ddr4_alert_n"] ;# Bank 66 VCCO - -Net DDR4_C0_ALERT_B - IO_L16P_T2U_N6_QBC_AD3P_66 set_property IOSTANDARD LVCMOS12 [get_ports "c0_ddr4_alert_n"] ;# Bank 66 VCCO - -Net DDR4_C0_ALERT_B - IO_L16P_T2U_N6_QBC_AD3P_66 set_property PACKAGE_PIN AT26 [get_ports "c0_ddr4_ba[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_BA0 - IO_L10P_T1U_N6_QBC_AD4P_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_ba[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_BA0 - IO_L10P_T1U_N6_QBC_AD4P_66 set_property PACKAGE_PIN AU27 [get_ports "c0_ddr4_ba[1]"] ;# Bank 66 VCCO - -Net DDR4_C0_BA1 - IO_L9P_T1L_N4_AD12P_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_ba[1]"] ;# Bank 66 VCCO - -Net DDR4_C0_BA1 - IO_L9P_T1L_N4_AD12P_66 set_property PACKAGE_PIN AU26 [get_ports "c0_ddr4_bg[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_BG0 - IO_L10N_T1U_N7_QBC_AD4N_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_bg[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_BG0 - IO_L10N_T1U_N7_QBC_AD4N_66 set_property PACKAGE_PIN AR28 [get_ports "c0_ddr4_adr[15]"] ;# Bank 66 VCCO - -Net DDR4_C0_CAS_B - IO_L8P_T1L_N2_AD5P_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[15]"] ;# Bank 66 VCCO - -Net DDR4_C0_CAS_B - IO_L8P_T1L_N2_AD5P_66 set_property PACKAGE_PIN AU30 [get_ports "c0_ddr4_ck_c[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_CK0_C - IO_L7N_T1L_N1_QBC_AD13N_66 set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "c0_ddr4_ck_c[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_CK0_C - IO_L7N_T1L_N1_QBC_AD13N_66 set_property PACKAGE_PIN AT29 [get_ports "c0_ddr4_ck_t[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_CK0_T - IO_L7P_T1L_N0_QBC_AD13P_66 set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "c0_ddr4_ck_t[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_CK0_T - IO_L7P_T1L_N0_QBC_AD13P_66 set_property PACKAGE_PIN AT28 [get_ports "c0_ddr4_cke[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_CKE0 - IO_L8N_T1L_N3_AD5N_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_cke[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_CKE0 - IO_L8N_T1L_N3_AD5N_66 set_property PACKAGE_PIN AL30 [get_ports "c0_ddr4_cs_n[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_CS0_B - IO_L1P_T0L_N0_DBC_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_cs_n[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_CS0_B - IO_L1P_T0L_N0_DBC_66 set_property PACKAGE_PIN AK29 [get_ports "c0_ddr4_dm_dbi_n[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_DM_B0 - IO_L19P_T3L_N0_DBC_AD9P_66 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_DM_B0 - IO_L19P_T3L_N0_DBC_AD9P_66 set_property PACKAGE_PIN AN37 [get_ports "c0_ddr4_dm_dbi_n[1]"] ;# Bank 67 VCCO - -Net DDR4_C0_DM_B1 - IO_L7P_T1L_N0_QBC_AD13P_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[1]"] ;# Bank 67 VCCO - -Net DDR4_C0_DM_B1 - IO_L7P_T1L_N0_QBC_AD13P_67 set_property PACKAGE_PIN Y33 [get_ports "c0_ddr4_dm_dbi_n[2]"] ;# Bank 68 VCCO - -Net DDR4_C0_DM_B2 - IO_L19P_T3L_N0_DBC_AD9P_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[2]"] ;# Bank 68 VCCO - -Net DDR4_C0_DM_B2 - IO_L19P_T3L_N0_DBC_AD9P_68 set_property PACKAGE_PIN AB36 [get_ports "c0_ddr4_dm_dbi_n[3]"] ;# Bank 68 VCCO - -Net DDR4_C0_DM_B3 - IO_L1P_T0L_N0_DBC_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[3]"] ;# Bank 68 VCCO - -Net DDR4_C0_DM_B3 - IO_L1P_T0L_N0_DBC_68 set_property PACKAGE_PIN AM36 [get_ports "c0_ddr4_dm_dbi_n[4]"] ;# Bank 67 VCCO - -Net DDR4_C0_DM_B4 - IO_L13P_T2L_N0_GC_QBC_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[4]"] ;# Bank 67 VCCO - -Net DDR4_C0_DM_B4 - IO_L13P_T2L_N0_GC_QBC_67 set_property PACKAGE_PIN AH37 [get_ports "c0_ddr4_dm_dbi_n[5]"] ;# Bank 67 VCCO - -Net DDR4_C0_DM_B5 - IO_L19P_T3L_N0_DBC_AD9P_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[5]"] ;# Bank 67 VCCO - -Net DDR4_C0_DM_B5 - IO_L19P_T3L_N0_DBC_AD9P_67 set_property PACKAGE_PIN AC37 [get_ports "c0_ddr4_dm_dbi_n[6]"] ;# Bank 68 VCCO - -Net DDR4_C0_DM_B6 - IO_L7P_T1L_N0_QBC_AD13P_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[6]"] ;# Bank 68 VCCO - -Net DDR4_C0_DM_B6 - IO_L7P_T1L_N0_QBC_AD13P_68 set_property PACKAGE_PIN AE32 [get_ports "c0_ddr4_dm_dbi_n[7]"] ;# Bank 68 VCCO - -Net DDR4_C0_DM_B7 - IO_L13P_T2L_N0_GC_QBC_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[7]"] ;# Bank 68 VCCO - -Net DDR4_C0_DM_B7 - IO_L13P_T2L_N0_GC_QBC_68 set_property PACKAGE_PIN AU31 [get_ports "c0_ddr4_dm_dbi_n[8]"] ;# Bank 67 VCCO - -Net DDR4_C0_DM_B8 - IO_L1P_T0L_N0_DBC_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[8]"] ;# Bank 67 VCCO - -Net DDR4_C0_DM_B8 - IO_L1P_T0L_N0_DBC_67 set_property PACKAGE_PIN AJ29 [get_ports "c0_ddr4_dq[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ0 - IO_L21N_T3L_N5_AD8N_66 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ0 - IO_L21N_T3L_N5_AD8N_66 set_property PACKAGE_PIN AR37 [get_ports "c0_ddr4_dq[10]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ10 - IO_L8N_T1L_N3_AD5N_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[10]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ10 - IO_L8N_T1L_N3_AD5N_67 set_property PACKAGE_PIN AN35 [get_ports "c0_ddr4_dq[11]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ11 - IO_L12N_T1U_N11_GC_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[11]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ11 - IO_L12N_T1U_N11_GC_67 set_property PACKAGE_PIN AN33 [get_ports "c0_ddr4_dq[12]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ12 - IO_L9P_T1L_N4_AD12P_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[12]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ12 - IO_L9P_T1L_N4_AD12P_67 set_property PACKAGE_PIN AN34 [get_ports "c0_ddr4_dq[13]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ13 - IO_L11N_T1U_N9_GC_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[13]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ13 - IO_L11N_T1U_N9_GC_67 set_property PACKAGE_PIN AP34 [get_ports "c0_ddr4_dq[14]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ14 - IO_L9N_T1L_N5_AD12N_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[14]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ14 - IO_L9N_T1L_N5_AD12N_67 set_property PACKAGE_PIN AM33 [get_ports "c0_ddr4_dq[15]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ15 - IO_L11P_T1U_N8_GC_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[15]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ15 - IO_L11P_T1U_N8_GC_67 set_property PACKAGE_PIN AA29 [get_ports "c0_ddr4_dq[16]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ16 - IO_L24N_T3U_N11_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[16]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ16 - IO_L24N_T3U_N11_68 set_property PACKAGE_PIN W32 [get_ports "c0_ddr4_dq[17]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ17 - IO_L20P_T3L_N2_AD1P_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[17]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ17 - IO_L20P_T3L_N2_AD1P_68 set_property PACKAGE_PIN Y32 [get_ports "c0_ddr4_dq[18]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ18 - IO_L20N_T3L_N3_AD1N_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[18]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ18 - IO_L20N_T3L_N3_AD1N_68 set_property PACKAGE_PIN W31 [get_ports "c0_ddr4_dq[19]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ19 - IO_L23N_T3U_N9_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[19]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ19 - IO_L23N_T3U_N9_68 set_property PACKAGE_PIN AJ31 [get_ports "c0_ddr4_dq[1]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ1 - IO_L20N_T3L_N3_AD1N_66 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[1]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ1 - IO_L20N_T3L_N3_AD1N_66 set_property PACKAGE_PIN AB32 [get_ports "c0_ddr4_dq[20]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ20 - IO_L21N_T3L_N5_AD8N_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[20]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ20 - IO_L21N_T3L_N5_AD8N_68 set_property PACKAGE_PIN W30 [get_ports "c0_ddr4_dq[21]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ21 - IO_L23P_T3U_N8_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[21]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ21 - IO_L23P_T3U_N8_68 set_property PACKAGE_PIN AB31 [get_ports "c0_ddr4_dq[22]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ22 - IO_L21P_T3L_N4_AD8P_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[22]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ22 - IO_L21P_T3L_N4_AD8P_68 set_property PACKAGE_PIN Y29 [get_ports "c0_ddr4_dq[23]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ23 - IO_L24P_T3U_N10_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[23]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ23 - IO_L24P_T3U_N10_68 set_property PACKAGE_PIN AA35 [get_ports "c0_ddr4_dq[24]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ24 - IO_L5N_T0U_N9_AD14N_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[24]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ24 - IO_L5N_T0U_N9_AD14N_68 set_property PACKAGE_PIN Y34 [get_ports "c0_ddr4_dq[25]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ25 - IO_L5P_T0U_N8_AD14P_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[25]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ25 - IO_L5P_T0U_N8_AD14P_68 set_property PACKAGE_PIN Y36 [get_ports "c0_ddr4_dq[26]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ26 - IO_L2P_T0L_N2_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[26]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ26 - IO_L2P_T0L_N2_68 set_property PACKAGE_PIN W37 [get_ports "c0_ddr4_dq[27]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ27 - IO_L3N_T0L_N5_AD15N_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[27]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ27 - IO_L3N_T0L_N5_AD15N_68 set_property PACKAGE_PIN AB35 [get_ports "c0_ddr4_dq[28]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ28 - IO_L6N_T0U_N11_AD6N_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[28]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ28 - IO_L6N_T0U_N11_AD6N_68 set_property PACKAGE_PIN AA34 [get_ports "c0_ddr4_dq[29]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ29 - IO_L6P_T0U_N10_AD6P_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[29]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ29 - IO_L6P_T0U_N10_AD6P_68 set_property PACKAGE_PIN AF30 [get_ports "c0_ddr4_dq[2]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ2 - IO_L23N_T3U_N9_66 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[2]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ2 - IO_L23N_T3U_N9_66 set_property PACKAGE_PIN AA36 [get_ports "c0_ddr4_dq[30]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ30 - IO_L2N_T0L_N3_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[30]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ30 - IO_L2N_T0L_N3_68 set_property PACKAGE_PIN W36 [get_ports "c0_ddr4_dq[31]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ31 - IO_L3P_T0L_N4_AD15P_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[31]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ31 - IO_L3P_T0L_N4_AD15P_68 set_property PACKAGE_PIN AL35 [get_ports "c0_ddr4_dq[32]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ32 - IO_L14P_T2L_N2_GC_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[32]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ32 - IO_L14P_T2L_N2_GC_67 set_property PACKAGE_PIN AK37 [get_ports "c0_ddr4_dq[33]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ33 - IO_L17N_T2U_N9_AD10N_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[33]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ33 - IO_L17N_T2U_N9_AD10N_67 set_property PACKAGE_PIN AL36 [get_ports "c0_ddr4_dq[34]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ34 - IO_L14N_T2L_N3_GC_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[34]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ34 - IO_L14N_T2L_N3_GC_67 set_property PACKAGE_PIN AK36 [get_ports "c0_ddr4_dq[35]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ35 - IO_L17P_T2U_N8_AD10P_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[35]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ35 - IO_L17P_T2U_N8_AD10P_67 set_property PACKAGE_PIN AL34 [get_ports "c0_ddr4_dq[36]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ36 - IO_L15N_T2L_N5_AD11N_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[36]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ36 - IO_L15N_T2L_N5_AD11N_67 set_property PACKAGE_PIN AJ35 [get_ports "c0_ddr4_dq[37]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ37 - IO_L18P_T2U_N10_AD2P_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[37]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ37 - IO_L18P_T2U_N10_AD2P_67 set_property PACKAGE_PIN AL33 [get_ports "c0_ddr4_dq[38]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ38 - IO_L15P_T2L_N4_AD11P_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[38]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ38 - IO_L15P_T2L_N4_AD11P_67 set_property PACKAGE_PIN AJ36 [get_ports "c0_ddr4_dq[39]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ39 - IO_L18N_T2U_N11_AD2N_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[39]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ39 - IO_L18N_T2U_N11_AD2N_67 set_property PACKAGE_PIN AF29 [get_ports "c0_ddr4_dq[3]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ3 - IO_L23P_T3U_N8_66 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[3]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ3 - IO_L23P_T3U_N8_66 set_property PACKAGE_PIN AG37 [get_ports "c0_ddr4_dq[40]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ40 - IO_L24N_T3U_N11_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[40]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ40 - IO_L24N_T3U_N11_67 set_property PACKAGE_PIN AH32 [get_ports "c0_ddr4_dq[41]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ41 - IO_L21P_T3L_N4_AD8P_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[41]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ41 - IO_L21P_T3L_N4_AD8P_67 set_property PACKAGE_PIN AH34 [get_ports "c0_ddr4_dq[42]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ42 - IO_L20P_T3L_N2_AD1P_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[42]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ42 - IO_L20P_T3L_N2_AD1P_67 set_property PACKAGE_PIN AG35 [get_ports "c0_ddr4_dq[43]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ43 - IO_L23P_T3U_N8_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[43]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ43 - IO_L23P_T3U_N8_67 set_property PACKAGE_PIN AH35 [get_ports "c0_ddr4_dq[44]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ44 - IO_L23N_T3U_N9_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[44]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ44 - IO_L23N_T3U_N9_67 set_property PACKAGE_PIN AJ32 [get_ports "c0_ddr4_dq[45]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ45 - IO_L21N_T3L_N5_AD8N_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[45]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ45 - IO_L21N_T3L_N5_AD8N_67 set_property PACKAGE_PIN AJ34 [get_ports "c0_ddr4_dq[46]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ46 - IO_L20N_T3L_N3_AD1N_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[46]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ46 - IO_L20N_T3L_N3_AD1N_67 set_property PACKAGE_PIN AG36 [get_ports "c0_ddr4_dq[47]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ47 - IO_L24P_T3U_N10_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[47]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ47 - IO_L24P_T3U_N10_67 set_property PACKAGE_PIN AE36 [get_ports "c0_ddr4_dq[48]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ48 - IO_L9P_T1L_N4_AD12P_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[48]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ48 - IO_L9P_T1L_N4_AD12P_68 set_property PACKAGE_PIN AF34 [get_ports "c0_ddr4_dq[49]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ49 - IO_L12N_T1U_N11_GC_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[49]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ49 - IO_L12N_T1U_N11_GC_68 set_property PACKAGE_PIN AH29 [get_ports "c0_ddr4_dq[4]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ4 - IO_L21P_T3L_N4_AD8P_66 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[4]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ4 - IO_L21P_T3L_N4_AD8P_66 set_property PACKAGE_PIN AD36 [get_ports "c0_ddr4_dq[50]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ50 - IO_L8P_T1L_N2_AD5P_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[50]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ50 - IO_L8P_T1L_N2_AD5P_68 set_property PACKAGE_PIN AC34 [get_ports "c0_ddr4_dq[51]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ51 - IO_L11P_T1U_N8_GC_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[51]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ51 - IO_L11P_T1U_N8_GC_68 set_property PACKAGE_PIN AF36 [get_ports "c0_ddr4_dq[52]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ52 - IO_L9N_T1L_N5_AD12N_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[52]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ52 - IO_L9N_T1L_N5_AD12N_68 set_property PACKAGE_PIN AE34 [get_ports "c0_ddr4_dq[53]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ53 - IO_L12P_T1U_N10_GC_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[53]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ53 - IO_L12P_T1U_N10_GC_68 set_property PACKAGE_PIN AE37 [get_ports "c0_ddr4_dq[54]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ54 - IO_L8N_T1L_N3_AD5N_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[54]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ54 - IO_L8N_T1L_N3_AD5N_68 set_property PACKAGE_PIN AD34 [get_ports "c0_ddr4_dq[55]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ55 - IO_L11N_T1U_N9_GC_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[55]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ55 - IO_L11N_T1U_N9_GC_68 set_property PACKAGE_PIN AB33 [get_ports "c0_ddr4_dq[56]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ56 - IO_L18P_T2U_N10_AD2P_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[56]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ56 - IO_L18P_T2U_N10_AD2P_68 set_property PACKAGE_PIN AD30 [get_ports "c0_ddr4_dq[57]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ57 - IO_L14P_T2L_N2_GC_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[57]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ57 - IO_L14P_T2L_N2_GC_68 set_property PACKAGE_PIN AC33 [get_ports "c0_ddr4_dq[58]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ58 - IO_L18N_T2U_N11_AD2N_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[58]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ58 - IO_L18N_T2U_N11_AD2N_68 set_property PACKAGE_PIN AD29 [get_ports "c0_ddr4_dq[59]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ59 - IO_L15N_T2L_N5_AD11N_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[59]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ59 - IO_L15N_T2L_N5_AD11N_68 set_property PACKAGE_PIN AG31 [get_ports "c0_ddr4_dq[5]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ5 - IO_L24N_T3U_N11_66 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[5]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ5 - IO_L24N_T3U_N11_66 set_property PACKAGE_PIN AE31 [get_ports "c0_ddr4_dq[60]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ60 - IO_L14N_T2L_N3_GC_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[60]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ60 - IO_L14N_T2L_N3_GC_68 set_property PACKAGE_PIN AC29 [get_ports "c0_ddr4_dq[61]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ61 - IO_L15P_T2L_N4_AD11P_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[61]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ61 - IO_L15P_T2L_N4_AD11P_68 set_property PACKAGE_PIN AD32 [get_ports "c0_ddr4_dq[62]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ62 - IO_L17N_T2U_N9_AD10N_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[62]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ62 - IO_L17N_T2U_N9_AD10N_68 set_property PACKAGE_PIN AC32 [get_ports "c0_ddr4_dq[63]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ63 - IO_L17P_T2U_N8_AD10P_68 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[63]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQ63 - IO_L17P_T2U_N8_AD10P_68 set_property PACKAGE_PIN AT33 [get_ports "c0_ddr4_dq[64]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ64 - IO_L2P_T0L_N2_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[64]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ64 - IO_L2P_T0L_N2_67 set_property PACKAGE_PIN AT36 [get_ports "c0_ddr4_dq[65]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ65 - IO_L5N_T0U_N9_AD14N_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[65]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ65 - IO_L5N_T0U_N9_AD14N_67 set_property PACKAGE_PIN AR33 [get_ports "c0_ddr4_dq[66]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ66 - IO_L3N_T0L_N5_AD15N_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[66]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ66 - IO_L3N_T0L_N5_AD15N_67 set_property PACKAGE_PIN AR36 [get_ports "c0_ddr4_dq[67]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ67 - IO_L6N_T0U_N11_AD6N_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[67]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ67 - IO_L6N_T0U_N11_AD6N_67 set_property PACKAGE_PIN AR32 [get_ports "c0_ddr4_dq[68]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ68 - IO_L3P_T0L_N4_AD15P_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[68]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ68 - IO_L3P_T0L_N4_AD15P_67 set_property PACKAGE_PIN AT35 [get_ports "c0_ddr4_dq[69]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ69 - IO_L5P_T0U_N8_AD14P_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[69]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ69 - IO_L5P_T0U_N8_AD14P_67 set_property PACKAGE_PIN AJ30 [get_ports "c0_ddr4_dq[6]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ6 - IO_L20P_T3L_N2_AD1P_66 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[6]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ6 - IO_L20P_T3L_N2_AD1P_66 set_property PACKAGE_PIN AU33 [get_ports "c0_ddr4_dq[70]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ70 - IO_L2N_T0L_N3_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[70]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ70 - IO_L2N_T0L_N3_67 set_property PACKAGE_PIN AP35 [get_ports "c0_ddr4_dq[71]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ71 - IO_L6P_T0U_N10_AD6P_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[71]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ71 - IO_L6P_T0U_N10_AD6P_67 set_property PACKAGE_PIN AF31 [get_ports "c0_ddr4_dq[7]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ7 - IO_L24P_T3U_N10_66 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[7]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQ7 - IO_L24P_T3U_N10_66 set_property PACKAGE_PIN AP36 [get_ports "c0_ddr4_dq[8]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ8 - IO_L8P_T1L_N2_AD5P_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[8]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ8 - IO_L8P_T1L_N2_AD5P_67 set_property PACKAGE_PIN AM35 [get_ports "c0_ddr4_dq[9]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ9 - IO_L12P_T1U_N10_GC_67 set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[9]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQ9 - IO_L12P_T1U_N10_GC_67 set_property PACKAGE_PIN AH30 [get_ports "c0_ddr4_dqs_c[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQS_C0 - IO_L22N_T3U_N7_DBC_AD0N_66 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQS_C0 - IO_L22N_T3U_N7_DBC_AD0N_66 set_property PACKAGE_PIN AN32 [get_ports "c0_ddr4_dqs_c[1]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_C1 - IO_L10N_T1U_N7_QBC_AD4N_67 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[1]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_C1 - IO_L10N_T1U_N7_QBC_AD4N_67 set_property PACKAGE_PIN AA31 [get_ports "c0_ddr4_dqs_c[2]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_C2 - IO_L22N_T3U_N7_DBC_AD0N_68 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[2]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_C2 - IO_L22N_T3U_N7_DBC_AD0N_68 set_property PACKAGE_PIN W35 [get_ports "c0_ddr4_dqs_c[3]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_C3 - IO_L4N_T0U_N7_DBC_AD7N_68 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[3]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_C3 - IO_L4N_T0U_N7_DBC_AD7N_68 set_property PACKAGE_PIN AK34 [get_ports "c0_ddr4_dqs_c[4]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_C4 - IO_L16N_T2U_N7_QBC_AD3N_67 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[4]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_C4 - IO_L16N_T2U_N7_QBC_AD3N_67 set_property PACKAGE_PIN AG33 [get_ports "c0_ddr4_dqs_c[5]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_C5 - IO_L22N_T3U_N7_DBC_AD0N_67 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[5]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_C5 - IO_L22N_T3U_N7_DBC_AD0N_67 set_property PACKAGE_PIN AD35 [get_ports "c0_ddr4_dqs_c[6]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_C6 - IO_L10N_T1U_N7_QBC_AD4N_68 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[6]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_C6 - IO_L10N_T1U_N7_QBC_AD4N_68 set_property PACKAGE_PIN AD31 [get_ports "c0_ddr4_dqs_c[7]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_C7 - IO_L16N_T2U_N7_QBC_AD3N_68 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[7]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_C7 - IO_L16N_T2U_N7_QBC_AD3N_68 set_property PACKAGE_PIN AU35 [get_ports "c0_ddr4_dqs_c[8]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_C8 - IO_L4N_T0U_N7_DBC_AD7N_67 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[8]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_C8 - IO_L4N_T0U_N7_DBC_AD7N_67 set_property PACKAGE_PIN AG30 [get_ports "c0_ddr4_dqs_t[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQS_T0 - IO_L22P_T3U_N6_DBC_AD0P_66 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_DQS_T0 - IO_L22P_T3U_N6_DBC_AD0P_66 set_property PACKAGE_PIN AM32 [get_ports "c0_ddr4_dqs_t[1]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_T1 - IO_L10P_T1U_N6_QBC_AD4P_67 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[1]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_T1 - IO_L10P_T1U_N6_QBC_AD4P_67 set_property PACKAGE_PIN Y31 [get_ports "c0_ddr4_dqs_t[2]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_T2 - IO_L22P_T3U_N6_DBC_AD0P_68 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[2]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_T2 - IO_L22P_T3U_N6_DBC_AD0P_68 set_property PACKAGE_PIN W34 [get_ports "c0_ddr4_dqs_t[3]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_T3 - IO_L4P_T0U_N6_DBC_AD7P_68 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[3]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_T3 - IO_L4P_T0U_N6_DBC_AD7P_68 set_property PACKAGE_PIN AK33 [get_ports "c0_ddr4_dqs_t[4]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_T4 - IO_L16P_T2U_N6_QBC_AD3P_67 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[4]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_T4 - IO_L16P_T2U_N6_QBC_AD3P_67 set_property PACKAGE_PIN AF33 [get_ports "c0_ddr4_dqs_t[5]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_T5 - IO_L22P_T3U_N6_DBC_AD0P_67 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[5]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_T5 - IO_L22P_T3U_N6_DBC_AD0P_67 set_property PACKAGE_PIN AC35 [get_ports "c0_ddr4_dqs_t[6]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_T6 - IO_L10P_T1U_N6_QBC_AD4P_68 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[6]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_T6 - IO_L10P_T1U_N6_QBC_AD4P_68 set_property PACKAGE_PIN AC30 [get_ports "c0_ddr4_dqs_t[7]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_T7 - IO_L16P_T2U_N6_QBC_AD3P_68 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[7]"] ;# Bank 68 VCCO - -Net DDR4_C0_DQS_T7 - IO_L16P_T2U_N6_QBC_AD3P_68 set_property PACKAGE_PIN AT34 [get_ports "c0_ddr4_dqs_t[8]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_T8 - IO_L4P_T0U_N6_DBC_AD7P_67 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[8]"] ;# Bank 67 VCCO - -Net DDR4_C0_DQS_T8 - IO_L4P_T0U_N6_DBC_AD7P_67 set_property PACKAGE_PIN AR31 [get_ports "c0_ddr4_odt[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_ODT0 - IO_L5P_T0U_N8_AD14P_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_odt[0]"] ;# Bank 66 VCCO - -Net DDR4_C0_ODT0 - IO_L5P_T0U_N8_AD14P_66 set_property PACKAGE_PIN AR29 [get_ports "c0_ddr4_parity[]"] ;# Bank 66 VCCO - -Net DDR4_C0_PARITY - IO_L6P_T0U_N10_AD6P_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_parity[]"] ;# Bank 66 VCCO - -Net DDR4_C0_PARITY - IO_L6P_T0U_N10_AD6P_66 set_property PACKAGE_PIN AU28 [get_ports "c0_ddr4_adr[16]"] ;# Bank 66 VCCO - -Net DDR4_C0_RAS_B - IO_L9N_T1L_N5_AD12N_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[16]"] ;# Bank 66 VCCO - -Net DDR4_C0_RAS_B - IO_L9N_T1L_N5_AD12N_66 set_property PACKAGE_PIN AK31 [get_ports "c0_ddr4_reset_n"] ;# Bank 66 VCCO - -Net DDR4_C0_RESET_B_FPGA - IO_T3U_N12_66 set_property IOSTANDARD LVCMOS12 [get_ports "c0_ddr4_reset_n"] ;# Bank 66 VCCO - -Net DDR4_C0_RESET_B_FPGA - IO_T3U_N12_66 set_property PACKAGE_PIN AR27 [get_ports "c0_ddr4_adr[14]"] ;# Bank 66 VCCO - -Net DDR4_C0_WE_B - IO_L11N_T1U_N9_GC_66 set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[14]"] ;# Bank 66 VCCO - -Net DDR4_C0_WE_B - IO_L11N_T1U_N9_GC_66 make_diff_pair_ports c0_ddr4_ck_t[0] c0_ddr4_ck_c[0] make_diff_pair_ports c0_ddr4_dqs_t[0] c0_ddr4_dqs_c[0] make_diff_pair_ports c0_ddr4_dqs_t[1] c0_ddr4_dqs_c[1] make_diff_pair_ports c0_ddr4_dqs_t[2] c0_ddr4_dqs_c[2] make_diff_pair_ports c0_ddr4_dqs_t[3] c0_ddr4_dqs_c[3] make_diff_pair_ports c0_ddr4_dqs_t[4] c0_ddr4_dqs_c[4] make_diff_pair_ports c0_ddr4_dqs_t[5] c0_ddr4_dqs_c[5] make_diff_pair_ports c0_ddr4_dqs_t[6] c0_ddr4_dqs_c[6] make_diff_pair_ports c0_ddr4_dqs_t[7] c0_ddr4_dqs_c[7] make_diff_pair_ports c0_ddr4_dqs_t[8] c0_ddr4_dqs_c[8] ################################################################################################################################################################## ## ## DDR4 DRAM Controller 2, Channel 1, 72-bit Data Interface, x16 data width ## ################################################################################################################################################################## set_property PACKAGE_PIN K32 [get_ports "c1_ddr4_adr[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_A0 - IO_L6P_T0U_N10_AD6P_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_A0 - IO_L6P_T0U_N10_AD6P_72 set_property PACKAGE_PIN J32 [get_ports "c1_ddr4_adr[10]"] ;# Bank 72 VCCO - -Net DDR4_C1_A10 - IO_L6N_T0U_N11_AD6N_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[10]"] ;# Bank 72 VCCO - -Net DDR4_C1_A10 - IO_L6N_T0U_N11_AD6N_72 set_property PACKAGE_PIN M36 [get_ports "c1_ddr4_adr[11]"] ;# Bank 72 VCCO - -Net DDR4_C1_A11 - IO_L8P_T1L_N2_AD5P_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[11]"] ;# Bank 72 VCCO - -Net DDR4_C1_A11 - IO_L8P_T1L_N2_AD5P_72 set_property PACKAGE_PIN H37 [get_ports "c1_ddr4_adr[12]"] ;# Bank 72 VCCO - -Net DDR4_C1_A12 - IO_L15P_T2L_N4_AD11P_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[12]"] ;# Bank 72 VCCO - -Net DDR4_C1_A12 - IO_L15P_T2L_N4_AD11P_72 set_property PACKAGE_PIN F36 [get_ports "c1_ddr4_adr[13]"] ;# Bank 72 VCCO - -Net DDR4_C1_A13 - IO_T2U_N12_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[13]"] ;# Bank 72 VCCO - -Net DDR4_C1_A13 - IO_T2U_N12_72 set_property PACKAGE_PIN K37 [get_ports "c1_ddr4_adr[1]"] ;# Bank 72 VCCO - -Net DDR4_C1_A1 - IO_L9P_T1L_N4_AD12P_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[1]"] ;# Bank 72 VCCO - -Net DDR4_C1_A1 - IO_L9P_T1L_N4_AD12P_72 set_property PACKAGE_PIN J31 [get_ports "c1_ddr4_adr[2]"] ;# Bank 72 VCCO - -Net DDR4_C1_A2 - IO_L5N_T0U_N9_AD14N_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[2]"] ;# Bank 72 VCCO - -Net DDR4_C1_A2 - IO_L5N_T0U_N9_AD14N_72 set_property PACKAGE_PIN J35 [get_ports "c1_ddr4_adr[3]"] ;# Bank 72 VCCO - -Net DDR4_C1_A3 - IO_L11P_T1U_N8_GC_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[3]"] ;# Bank 72 VCCO - -Net DDR4_C1_A3 - IO_L11P_T1U_N8_GC_72 set_property PACKAGE_PIN L34 [get_ports "c1_ddr4_adr[4]"] ;# Bank 72 VCCO - -Net DDR4_C1_A4 - IO_L10P_T1U_N6_QBC_AD4P_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[4]"] ;# Bank 72 VCCO - -Net DDR4_C1_A4 - IO_L10P_T1U_N6_QBC_AD4P_72 set_property PACKAGE_PIN E37 [get_ports "c1_ddr4_adr[5]"] ;# Bank 72 VCCO - -Net DDR4_C1_A5 - IO_L17N_T2U_N9_AD10N_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[5]"] ;# Bank 72 VCCO - -Net DDR4_C1_A5 - IO_L17N_T2U_N9_AD10N_72 set_property PACKAGE_PIN L36 [get_ports "c1_ddr4_adr[6]"] ;# Bank 72 VCCO - -Net DDR4_C1_A6 - IO_L7N_T1L_N1_QBC_AD13N_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[6]"] ;# Bank 72 VCCO - -Net DDR4_C1_A6 - IO_L7N_T1L_N1_QBC_AD13N_72 set_property PACKAGE_PIN F35 [get_ports "c1_ddr4_adr[7]"] ;# Bank 72 VCCO - -Net DDR4_C1_A7 - IO_L16N_T2U_N7_QBC_AD3N_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[7]"] ;# Bank 72 VCCO - -Net DDR4_C1_A7 - IO_L16N_T2U_N7_QBC_AD3N_72 set_property PACKAGE_PIN M35 [get_ports "c1_ddr4_adr[8]"] ;# Bank 72 VCCO - -Net DDR4_C1_A8 - IO_L7P_T1L_N0_QBC_AD13P_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[8]"] ;# Bank 72 VCCO - -Net DDR4_C1_A8 - IO_L7P_T1L_N0_QBC_AD13P_72 set_property PACKAGE_PIN M37 [get_ports "c1_ddr4_adr[9]"] ;# Bank 72 VCCO - -Net DDR4_C1_A9 - IO_L8N_T1L_N3_AD5N_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[9]"] ;# Bank 72 VCCO - -Net DDR4_C1_A9 - IO_L8N_T1L_N3_AD5N_72 set_property PACKAGE_PIN J34 [get_ports "c1_ddr4_act_n"] ;# Bank 72 VCCO - -Net DDR4_C1_ACT_B - IO_L12N_T1U_N11_GC_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_act_n"] ;# Bank 72 VCCO - -Net DDR4_C1_ACT_B - IO_L12N_T1U_N11_GC_72 set_property PACKAGE_PIN L35 [get_ports "c1_ddr4_alert_n"] ;# Bank 72 VCCO - -Net DDR4_C1_ALERT_B - IO_L10N_T1U_N7_QBC_AD4N_72 set_property IOSTANDARD LVCMOS12 [get_ports "c1_ddr4_alert_n"] ;# Bank 72 VCCO - -Net DDR4_C1_ALERT_B - IO_L10N_T1U_N7_QBC_AD4N_72 set_property PACKAGE_PIN K36 [get_ports "c1_ddr4_ba[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_BA0 - IO_T1U_N12_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_ba[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_BA0 - IO_T1U_N12_72 set_property PACKAGE_PIN E36 [get_ports "c1_ddr4_ba[1]"] ;# Bank 72 VCCO - -Net DDR4_C1_BA1 - IO_L17P_T2U_N8_AD10P_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_ba[1]"] ;# Bank 72 VCCO - -Net DDR4_C1_BA1 - IO_L17P_T2U_N8_AD10P_72 set_property PACKAGE_PIN J36 [get_ports "c1_ddr4_bg[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_BG0 - IO_L11N_T1U_N9_GC_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_bg[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_BG0 - IO_L11N_T1U_N9_GC_72 set_property PACKAGE_PIN E34 [get_ports "c1_ddr4_adr[15]"] ;# Bank 72 VCCO - -Net DDR4_C1_CAS_B - IO_L18P_T2U_N10_AD2P_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[15]"] ;# Bank 72 VCCO - -Net DDR4_C1_CAS_B - IO_L18P_T2U_N10_AD2P_72 set_property PACKAGE_PIN G36 [get_ports "c1_ddr4_ck_c[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_CK0_C - IO_L14N_T2L_N3_GC_72 set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "c1_ddr4_ck_c[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_CK0_C - IO_L14N_T2L_N3_GC_72 set_property PACKAGE_PIN G35 [get_ports "c1_ddr4_ck_t[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_CK0_T - IO_L14P_T2L_N2_GC_72 set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "c1_ddr4_ck_t[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_CK0_T - IO_L14P_T2L_N2_GC_72 set_property PACKAGE_PIN K29 [get_ports "c1_ddr4_cke[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_CKE0 - IO_L4P_T0U_N6_DBC_AD7P_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_cke[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_CKE0 - IO_L4P_T0U_N6_DBC_AD7P_72 set_property PACKAGE_PIN G37 [get_ports "c1_ddr4_cs_n[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_CS0_B - IO_L15N_T2L_N5_AD11N_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_cs_n[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_CS0_B - IO_L15N_T2L_N5_AD11N_72 set_property PACKAGE_PIN C28 [get_ports "c1_ddr4_dm_dbi_n[0]"] ;# Bank 73 VCCO - -Net DDR4_C1_DM_B0 - IO_L19P_T3L_N0_DBC_AD9P_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dm_dbi_n[0]"] ;# Bank 73 VCCO - -Net DDR4_C1_DM_B0 - IO_L19P_T3L_N0_DBC_AD9P_73 set_property PACKAGE_PIN H25 [get_ports "c1_ddr4_dm_dbi_n[1]"] ;# Bank 73 VCCO - -Net DDR4_C1_DM_B1 - IO_L1P_T0L_N0_DBC_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dm_dbi_n[1]"] ;# Bank 73 VCCO - -Net DDR4_C1_DM_B1 - IO_L1P_T0L_N0_DBC_73 set_property PACKAGE_PIN E32 [get_ports "c1_ddr4_dm_dbi_n[2]"] ;# Bank 73 VCCO - -Net DDR4_C1_DM_B2 - IO_L13P_T2L_N0_GC_QBC_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dm_dbi_n[2]"] ;# Bank 73 VCCO - -Net DDR4_C1_DM_B2 - IO_L13P_T2L_N0_GC_QBC_73 set_property PACKAGE_PIN H32 [get_ports "c1_ddr4_dm_dbi_n[3]"] ;# Bank 73 VCCO - -Net DDR4_C1_DM_B3 - IO_L7P_T1L_N0_QBC_AD13P_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dm_dbi_n[3]"] ;# Bank 73 VCCO - -Net DDR4_C1_DM_B3 - IO_L7P_T1L_N0_QBC_AD13P_73 set_property PACKAGE_PIN E23 [get_ports "c1_ddr4_dm_dbi_n[4]"] ;# Bank 74 VCCO - -Net DDR4_C1_DM_B4 - IO_L19P_T3L_N0_DBC_AD9P_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dm_dbi_n[4]"] ;# Bank 74 VCCO - -Net DDR4_C1_DM_B4 - IO_L19P_T3L_N0_DBC_AD9P_74 set_property PACKAGE_PIN H22 [get_ports "c1_ddr4_dm_dbi_n[5]"] ;# Bank 74 VCCO - -Net DDR4_C1_DM_B5 - IO_L7P_T1L_N0_QBC_AD13P_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dm_dbi_n[5]"] ;# Bank 74 VCCO - -Net DDR4_C1_DM_B5 - IO_L7P_T1L_N0_QBC_AD13P_74 set_property PACKAGE_PIN H14 [get_ports "c1_ddr4_dm_dbi_n[6]"] ;# Bank 74 VCCO - -Net DDR4_C1_DM_B6 - IO_L1P_T0L_N0_DBC_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dm_dbi_n[6]"] ;# Bank 74 VCCO - -Net DDR4_C1_DM_B6 - IO_L1P_T0L_N0_DBC_74 set_property PACKAGE_PIN E18 [get_ports "c1_ddr4_dm_dbi_n[7]"] ;# Bank 74 VCCO - -Net DDR4_C1_DM_B7 - IO_L13P_T2L_N0_GC_QBC_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dm_dbi_n[7]"] ;# Bank 74 VCCO - -Net DDR4_C1_DM_B7 - IO_L13P_T2L_N0_GC_QBC_74 set_property PACKAGE_PIN D35 [get_ports "c1_ddr4_dm_dbi_n[8]"] ;# Bank 72 VCCO - -Net DDR4_C1_DM_B8 - IO_L19P_T3L_N0_DBC_AD9P_72 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dm_dbi_n[8]"] ;# Bank 72 VCCO - -Net DDR4_C1_DM_B8 - IO_L19P_T3L_N0_DBC_AD9P_72 set_property PACKAGE_PIN A28 [get_ports "c1_ddr4_dq[0]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ0 - IO_L23P_T3U_N8_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[0]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ0 - IO_L23P_T3U_N8_73 set_property PACKAGE_PIN H27 [get_ports "c1_ddr4_dq[10]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ10 - IO_L3P_T0L_N4_AD15P_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[10]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ10 - IO_L3P_T0L_N4_AD15P_73 set_property PACKAGE_PIN F28 [get_ports "c1_ddr4_dq[11]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ11 - IO_L6P_T0U_N10_AD6P_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[11]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ11 - IO_L6P_T0U_N10_AD6P_73 set_property PACKAGE_PIN E27 [get_ports "c1_ddr4_dq[12]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ12 - IO_L5N_T0U_N9_AD14N_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[12]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ12 - IO_L5N_T0U_N9_AD14N_73 set_property PACKAGE_PIN F26 [get_ports "c1_ddr4_dq[13]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ13 - IO_L2N_T0L_N3_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[13]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ13 - IO_L2N_T0L_N3_73 set_property PACKAGE_PIN G26 [get_ports "c1_ddr4_dq[14]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ14 - IO_L2P_T0L_N2_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[14]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ14 - IO_L2P_T0L_N2_73 set_property PACKAGE_PIN E28 [get_ports "c1_ddr4_dq[15]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ15 - IO_L6N_T0U_N11_AD6N_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[15]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ15 - IO_L6N_T0U_N11_AD6N_73 set_property PACKAGE_PIN D30 [get_ports "c1_ddr4_dq[16]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ16 - IO_L14P_T2L_N2_GC_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[16]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ16 - IO_L14P_T2L_N2_GC_73 set_property PACKAGE_PIN A30 [get_ports "c1_ddr4_dq[17]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ17 - IO_L18P_T2U_N10_AD2P_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[17]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ17 - IO_L18P_T2U_N10_AD2P_73 set_property PACKAGE_PIN A31 [get_ports "c1_ddr4_dq[18]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ18 - IO_L18N_T2U_N11_AD2N_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[18]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ18 - IO_L18N_T2U_N11_AD2N_73 set_property PACKAGE_PIN B30 [get_ports "c1_ddr4_dq[19]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ19 - IO_L17N_T2U_N9_AD10N_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[19]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ19 - IO_L17N_T2U_N9_AD10N_73 set_property PACKAGE_PIN C25 [get_ports "c1_ddr4_dq[1]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ1 - IO_L21N_T3L_N5_AD8N_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[1]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ1 - IO_L21N_T3L_N5_AD8N_73 set_property PACKAGE_PIN D31 [get_ports "c1_ddr4_dq[20]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ20 - IO_L14N_T2L_N3_GC_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[20]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ20 - IO_L14N_T2L_N3_GC_73 set_property PACKAGE_PIN C30 [get_ports "c1_ddr4_dq[21]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ21 - IO_L17P_T2U_N8_AD10P_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[21]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ21 - IO_L17P_T2U_N8_AD10P_73 set_property PACKAGE_PIN E29 [get_ports "c1_ddr4_dq[22]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ22 - IO_L15P_T2L_N4_AD11P_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[22]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ22 - IO_L15P_T2L_N4_AD11P_73 set_property PACKAGE_PIN D29 [get_ports "c1_ddr4_dq[23]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ23 - IO_L15N_T2L_N5_AD11N_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[23]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ23 - IO_L15N_T2L_N5_AD11N_73 set_property PACKAGE_PIN E33 [get_ports "c1_ddr4_dq[24]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ24 - IO_L9N_T1L_N5_AD12N_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[24]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ24 - IO_L9N_T1L_N5_AD12N_73 set_property PACKAGE_PIN F29 [get_ports "c1_ddr4_dq[25]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ25 - IO_L11P_T1U_N8_GC_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[25]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ25 - IO_L11P_T1U_N8_GC_73 set_property PACKAGE_PIN F33 [get_ports "c1_ddr4_dq[26]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ26 - IO_L9P_T1L_N4_AD12P_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[26]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ26 - IO_L9P_T1L_N4_AD12P_73 set_property PACKAGE_PIN F30 [get_ports "c1_ddr4_dq[27]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ27 - IO_L11N_T1U_N9_GC_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[27]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ27 - IO_L11N_T1U_N9_GC_73 set_property PACKAGE_PIN H33 [get_ports "c1_ddr4_dq[28]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ28 - IO_L8P_T1L_N2_AD5P_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[28]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ28 - IO_L8P_T1L_N2_AD5P_73 set_property PACKAGE_PIN E31 [get_ports "c1_ddr4_dq[29]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ29 - IO_L12N_T1U_N11_GC_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[29]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ29 - IO_L12N_T1U_N11_GC_73 set_property PACKAGE_PIN A26 [get_ports "c1_ddr4_dq[2]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ2 - IO_L24N_T3U_N11_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[2]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ2 - IO_L24N_T3U_N11_73 set_property PACKAGE_PIN G33 [get_ports "c1_ddr4_dq[30]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ30 - IO_L8N_T1L_N3_AD5N_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[30]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ30 - IO_L8N_T1L_N3_AD5N_73 set_property PACKAGE_PIN F31 [get_ports "c1_ddr4_dq[31]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ31 - IO_L12P_T1U_N10_GC_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[31]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ31 - IO_L12P_T1U_N10_GC_73 set_property PACKAGE_PIN B25 [get_ports "c1_ddr4_dq[32]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ32 - IO_L24P_T3U_N10_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[32]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ32 - IO_L24P_T3U_N10_74 set_property PACKAGE_PIN C22 [get_ports "c1_ddr4_dq[33]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ33 - IO_L20N_T3L_N3_AD1N_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[33]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ33 - IO_L20N_T3L_N3_AD1N_74 set_property PACKAGE_PIN A23 [get_ports "c1_ddr4_dq[34]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ34 - IO_L23P_T3U_N8_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[34]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ34 - IO_L23P_T3U_N8_74 set_property PACKAGE_PIN A24 [get_ports "c1_ddr4_dq[35]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ35 - IO_L23N_T3U_N9_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[35]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ35 - IO_L23N_T3U_N9_74 set_property PACKAGE_PIN A25 [get_ports "c1_ddr4_dq[36]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ36 - IO_L24N_T3U_N11_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[36]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ36 - IO_L24N_T3U_N11_74 set_property PACKAGE_PIN D24 [get_ports "c1_ddr4_dq[37]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ37 - IO_L21P_T3L_N4_AD8P_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[37]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ37 - IO_L21P_T3L_N4_AD8P_74 set_property PACKAGE_PIN C24 [get_ports "c1_ddr4_dq[38]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ38 - IO_L21N_T3L_N5_AD8N_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[38]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ38 - IO_L21N_T3L_N5_AD8N_74 set_property PACKAGE_PIN D22 [get_ports "c1_ddr4_dq[39]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ39 - IO_L20P_T3L_N2_AD1P_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[39]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ39 - IO_L20P_T3L_N2_AD1P_74 set_property PACKAGE_PIN D25 [get_ports "c1_ddr4_dq[3]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ3 - IO_L21P_T3L_N4_AD8P_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[3]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ3 - IO_L21P_T3L_N4_AD8P_73 set_property PACKAGE_PIN F23 [get_ports "c1_ddr4_dq[40]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ40 - IO_L9P_T1L_N4_AD12P_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[40]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ40 - IO_L9P_T1L_N4_AD12P_74 set_property PACKAGE_PIN G21 [get_ports "c1_ddr4_dq[41]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ41 - IO_L11P_T1U_N8_GC_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[41]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ41 - IO_L11P_T1U_N8_GC_74 set_property PACKAGE_PIN F24 [get_ports "c1_ddr4_dq[42]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ42 - IO_L9N_T1L_N5_AD12N_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[42]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ42 - IO_L9N_T1L_N5_AD12N_74 set_property PACKAGE_PIN F20 [get_ports "c1_ddr4_dq[43]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ43 - IO_L12N_T1U_N11_GC_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[43]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ43 - IO_L12N_T1U_N11_GC_74 set_property PACKAGE_PIN H23 [get_ports "c1_ddr4_dq[44]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ44 - IO_L8P_T1L_N2_AD5P_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[44]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ44 - IO_L8P_T1L_N2_AD5P_74 set_property PACKAGE_PIN F19 [get_ports "c1_ddr4_dq[45]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ45 - IO_L12P_T1U_N10_GC_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[45]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ45 - IO_L12P_T1U_N10_GC_74 set_property PACKAGE_PIN H24 [get_ports "c1_ddr4_dq[46]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ46 - IO_L8N_T1L_N3_AD5N_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[46]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ46 - IO_L8N_T1L_N3_AD5N_74 set_property PACKAGE_PIN F21 [get_ports "c1_ddr4_dq[47]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ47 - IO_L11N_T1U_N9_GC_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[47]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ47 - IO_L11N_T1U_N9_GC_74 set_property PACKAGE_PIN G18 [get_ports "c1_ddr4_dq[48]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ48 - IO_L6P_T0U_N10_AD6P_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[48]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ48 - IO_L6P_T0U_N10_AD6P_74 set_property PACKAGE_PIN G17 [get_ports "c1_ddr4_dq[49]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ49 - IO_L3N_T0L_N5_AD15N_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[49]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ49 - IO_L3N_T0L_N5_AD15N_74 set_property PACKAGE_PIN A29 [get_ports "c1_ddr4_dq[4]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ4 - IO_L23N_T3U_N9_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[4]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ4 - IO_L23N_T3U_N9_73 set_property PACKAGE_PIN F16 [get_ports "c1_ddr4_dq[50]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ50 - IO_L5P_T0U_N8_AD14P_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[50]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ50 - IO_L5P_T0U_N8_AD14P_74 set_property PACKAGE_PIN G16 [get_ports "c1_ddr4_dq[51]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ51 - IO_L3P_T0L_N4_AD15P_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[51]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ51 - IO_L3P_T0L_N4_AD15P_74 set_property PACKAGE_PIN F18 [get_ports "c1_ddr4_dq[52]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ52 - IO_L6N_T0U_N11_AD6N_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[52]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ52 - IO_L6N_T0U_N11_AD6N_74 set_property PACKAGE_PIN H15 [get_ports "c1_ddr4_dq[53]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ53 - IO_L2P_T0L_N2_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[53]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ53 - IO_L2P_T0L_N2_74 set_property PACKAGE_PIN E16 [get_ports "c1_ddr4_dq[54]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ54 - IO_L5N_T0U_N9_AD14N_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[54]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ54 - IO_L5N_T0U_N9_AD14N_74 set_property PACKAGE_PIN G15 [get_ports "c1_ddr4_dq[55]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ55 - IO_L2N_T0L_N3_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[55]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ55 - IO_L2N_T0L_N3_74 set_property PACKAGE_PIN B21 [get_ports "c1_ddr4_dq[56]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ56 - IO_L18P_T2U_N10_AD2P_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[56]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ56 - IO_L18P_T2U_N10_AD2P_74 set_property PACKAGE_PIN D20 [get_ports "c1_ddr4_dq[57]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ57 - IO_L14P_T2L_N2_GC_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[57]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ57 - IO_L14P_T2L_N2_GC_74 set_property PACKAGE_PIN A21 [get_ports "c1_ddr4_dq[58]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ58 - IO_L18N_T2U_N11_AD2N_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[58]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ58 - IO_L18N_T2U_N11_AD2N_74 set_property PACKAGE_PIN B20 [get_ports "c1_ddr4_dq[59]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ59 - IO_L17P_T2U_N8_AD10P_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[59]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ59 - IO_L17P_T2U_N8_AD10P_74 set_property PACKAGE_PIN D27 [get_ports "c1_ddr4_dq[5]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ5 - IO_L20N_T3L_N3_AD1N_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[5]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ5 - IO_L20N_T3L_N3_AD1N_73 set_property PACKAGE_PIN E22 [get_ports "c1_ddr4_dq[60]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ60 - IO_L15N_T2L_N5_AD11N_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[60]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ60 - IO_L15N_T2L_N5_AD11N_74 set_property PACKAGE_PIN C20 [get_ports "c1_ddr4_dq[61]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ61 - IO_L14N_T2L_N3_GC_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[61]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ61 - IO_L14N_T2L_N3_GC_74 set_property PACKAGE_PIN E21 [get_ports "c1_ddr4_dq[62]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ62 - IO_L15P_T2L_N4_AD11P_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[62]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ62 - IO_L15P_T2L_N4_AD11P_74 set_property PACKAGE_PIN A20 [get_ports "c1_ddr4_dq[63]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ63 - IO_L17N_T2U_N9_AD10N_74 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[63]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQ63 - IO_L17N_T2U_N9_AD10N_74 set_property PACKAGE_PIN C37 [get_ports "c1_ddr4_dq[64]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ64 - IO_L20N_T3L_N3_AD1N_72 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[64]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ64 - IO_L20N_T3L_N3_AD1N_72 set_property PACKAGE_PIN A34 [get_ports "c1_ddr4_dq[65]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ65 - IO_L23P_T3U_N8_72 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[65]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ65 - IO_L23P_T3U_N8_72 set_property PACKAGE_PIN C35 [get_ports "c1_ddr4_dq[66]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ66 - IO_L21N_T3L_N5_AD8N_72 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[66]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ66 - IO_L21N_T3L_N5_AD8N_72 set_property PACKAGE_PIN C34 [get_ports "c1_ddr4_dq[67]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ67 - IO_L21P_T3L_N4_AD8P_72 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[67]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ67 - IO_L21P_T3L_N4_AD8P_72 set_property PACKAGE_PIN D37 [get_ports "c1_ddr4_dq[68]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ68 - IO_L20P_T3L_N2_AD1P_72 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[68]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ68 - IO_L20P_T3L_N2_AD1P_72 set_property PACKAGE_PIN B33 [get_ports "c1_ddr4_dq[69]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ69 - IO_L24P_T3U_N10_72 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[69]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ69 - IO_L24P_T3U_N10_72 set_property PACKAGE_PIN B26 [get_ports "c1_ddr4_dq[6]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ6 - IO_L24P_T3U_N10_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[6]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ6 - IO_L24P_T3U_N10_73 set_property PACKAGE_PIN A35 [get_ports "c1_ddr4_dq[70]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ70 - IO_L23N_T3U_N9_72 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[70]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ70 - IO_L23N_T3U_N9_72 set_property PACKAGE_PIN A33 [get_ports "c1_ddr4_dq[71]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ71 - IO_L24N_T3U_N11_72 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[71]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQ71 - IO_L24N_T3U_N11_72 set_property PACKAGE_PIN D26 [get_ports "c1_ddr4_dq[7]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ7 - IO_L20P_T3L_N2_AD1P_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[7]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ7 - IO_L20P_T3L_N2_AD1P_73 set_property PACKAGE_PIN G27 [get_ports "c1_ddr4_dq[8]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ8 - IO_L3N_T0L_N5_AD15N_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[8]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ8 - IO_L3N_T0L_N5_AD15N_73 set_property PACKAGE_PIN E26 [get_ports "c1_ddr4_dq[9]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ9 - IO_L5P_T0U_N8_AD14P_73 set_property IOSTANDARD POD12_DCI [get_ports "c1_ddr4_dq[9]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQ9 - IO_L5P_T0U_N8_AD14P_73 set_property PACKAGE_PIN B28 [get_ports "c1_ddr4_dqs_c[0]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_C0 - IO_L22N_T3U_N7_DBC_AD0N_73 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_c[0]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_C0 - IO_L22N_T3U_N7_DBC_AD0N_73 set_property PACKAGE_PIN G28 [get_ports "c1_ddr4_dqs_c[1]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_C1 - IO_L4N_T0U_N7_DBC_AD7N_73 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_c[1]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_C1 - IO_L4N_T0U_N7_DBC_AD7N_73 set_property PACKAGE_PIN B32 [get_ports "c1_ddr4_dqs_c[2]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_C2 - IO_L16N_T2U_N7_QBC_AD3N_73 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_c[2]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_C2 - IO_L16N_T2U_N7_QBC_AD3N_73 set_property PACKAGE_PIN G31 [get_ports "c1_ddr4_dqs_c[3]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_C3 - IO_L10N_T1U_N7_QBC_AD4N_73 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_c[3]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_C3 - IO_L10N_T1U_N7_QBC_AD4N_73 set_property PACKAGE_PIN B23 [get_ports "c1_ddr4_dqs_c[4]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_C4 - IO_L22N_T3U_N7_DBC_AD0N_74 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_c[4]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_C4 - IO_L22N_T3U_N7_DBC_AD0N_74 set_property PACKAGE_PIN H20 [get_ports "c1_ddr4_dqs_c[5]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_C5 - IO_L10N_T1U_N7_QBC_AD4N_74 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_c[5]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_C5 - IO_L10N_T1U_N7_QBC_AD4N_74 set_property PACKAGE_PIN H18 [get_ports "c1_ddr4_dqs_c[6]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_C6 - IO_L4N_T0U_N7_DBC_AD7N_74 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_c[6]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_C6 - IO_L4N_T0U_N7_DBC_AD7N_74 set_property PACKAGE_PIN A19 [get_ports "c1_ddr4_dqs_c[7]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_C7 - IO_L16N_T2U_N7_QBC_AD3N_74 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_c[7]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_C7 - IO_L16N_T2U_N7_QBC_AD3N_74 set_property PACKAGE_PIN B36 [get_ports "c1_ddr4_dqs_c[8]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQS_C8 - IO_L22N_T3U_N7_DBC_AD0N_72 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_c[8]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQS_C8 - IO_L22N_T3U_N7_DBC_AD0N_72 set_property PACKAGE_PIN B27 [get_ports "c1_ddr4_dqs_t[0]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_T0 - IO_L22P_T3U_N6_DBC_AD0P_73 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_t[0]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_T0 - IO_L22P_T3U_N6_DBC_AD0P_73 set_property PACKAGE_PIN H28 [get_ports "c1_ddr4_dqs_t[1]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_T1 - IO_L4P_T0U_N6_DBC_AD7P_73 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_t[1]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_T1 - IO_L4P_T0U_N6_DBC_AD7P_73 set_property PACKAGE_PIN C32 [get_ports "c1_ddr4_dqs_t[2]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_T2 - IO_L16P_T2U_N6_QBC_AD3P_73 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_t[2]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_T2 - IO_L16P_T2U_N6_QBC_AD3P_73 set_property PACKAGE_PIN G30 [get_ports "c1_ddr4_dqs_t[3]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_T3 - IO_L10P_T1U_N6_QBC_AD4P_73 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_t[3]"] ;# Bank 73 VCCO - -Net DDR4_C1_DQS_T3 - IO_L10P_T1U_N6_QBC_AD4P_73 set_property PACKAGE_PIN B22 [get_ports "c1_ddr4_dqs_t[4]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_T4 - IO_L22P_T3U_N6_DBC_AD0P_74 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_t[4]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_T4 - IO_L22P_T3U_N6_DBC_AD0P_74 set_property PACKAGE_PIN H19 [get_ports "c1_ddr4_dqs_t[5]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_T5 - IO_L10P_T1U_N6_QBC_AD4P_74 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_t[5]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_T5 - IO_L10P_T1U_N6_QBC_AD4P_74 set_property PACKAGE_PIN H17 [get_ports "c1_ddr4_dqs_t[6]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_T6 - IO_L4P_T0U_N6_DBC_AD7P_74 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_t[6]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_T6 - IO_L4P_T0U_N6_DBC_AD7P_74 set_property PACKAGE_PIN A18 [get_ports "c1_ddr4_dqs_t[7]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_T7 - IO_L16P_T2U_N6_QBC_AD3P_74 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_t[7]"] ;# Bank 74 VCCO - -Net DDR4_C1_DQS_T7 - IO_L16P_T2U_N6_QBC_AD3P_74 set_property PACKAGE_PIN B35 [get_ports "c1_ddr4_dqs_t[8]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQS_T8 - IO_L22P_T3U_N6_DBC_AD0P_72 set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c1_ddr4_dqs_t[8]"] ;# Bank 72 VCCO - -Net DDR4_C1_DQS_T8 - IO_L22P_T3U_N6_DBC_AD0P_72 set_property PACKAGE_PIN J37 [get_ports "c1_ddr4_odt[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_ODT0 - IO_L9N_T1L_N5_AD12N_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_odt[0]"] ;# Bank 72 VCCO - -Net DDR4_C1_ODT0 - IO_L9N_T1L_N5_AD12N_72 set_property PACKAGE_PIN J30 [get_ports "c1_ddr4_parity[]"] ;# Bank 72 VCCO - -Net DDR4_C1_PARITY - IO_L5P_T0U_N8_AD14P_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_parity[]"] ;# Bank 72 VCCO - -Net DDR4_C1_PARITY - IO_L5P_T0U_N8_AD14P_72 set_property PACKAGE_PIN D34 [get_ports "c1_ddr4_adr[16]"] ;# Bank 72 VCCO - -Net DDR4_C1_RAS_B - IO_L18N_T2U_N11_AD2N_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[16]"] ;# Bank 72 VCCO - -Net DDR4_C1_RAS_B - IO_L18N_T2U_N11_AD2N_72 set_property PACKAGE_PIN L29 [get_ports "c1_ddr4_reset_n"] ;# Bank 72 VCCO - -Net DDR4_C1_RESET_B_FPGA - IO_L1P_T0L_N0_DBC_72 set_property IOSTANDARD LVCMOS12 [get_ports "c1_ddr4_reset_n"] ;# Bank 72 VCCO - -Net DDR4_C1_RESET_B_FPGA - IO_L1P_T0L_N0_DBC_72 set_property PACKAGE_PIN M32 [get_ports "c1_ddr4_adr[14]"] ;# Bank 72 VCCO - -Net DDR4_C1_WE_B - IO_L2P_T0L_N2_72 set_property IOSTANDARD SSTL12_DCI [get_ports "c1_ddr4_adr[14]"] ;# Bank 72 VCCO - -Net DDR4_C1_WE_B - IO_L2P_T0L_N2_72 make_diff_pair_ports c1_ddr4_ck_t[0] c1_ddr4_ck_c[0] make_diff_pair_ports c1_ddr4_dqs_t[0] c1_ddr4_dqs_c[0] make_diff_pair_ports c1_ddr4_dqs_t[1] c1_ddr4_dqs_c[1] make_diff_pair_ports c1_ddr4_dqs_t[2] c1_ddr4_dqs_c[2] make_diff_pair_ports c1_ddr4_dqs_t[3] c1_ddr4_dqs_c[3] make_diff_pair_ports c1_ddr4_dqs_t[4] c1_ddr4_dqs_c[4] make_diff_pair_ports c1_ddr4_dqs_t[5] c1_ddr4_dqs_c[5] make_diff_pair_ports c1_ddr4_dqs_t[6] c1_ddr4_dqs_c[6] make_diff_pair_ports c1_ddr4_dqs_t[7] c1_ddr4_dqs_c[7] make_diff_pair_ports c1_ddr4_dqs_t[8] c1_ddr4_dqs_c[8] ################################################################################################################################################################## # # GTY Lanes Connected from FPGA to ARM SOC Single 25G Interface # ################################################################################################################################################################## set_property SEVERITY {Warning} [get_drc_checks GTYCHK-1] set_property SEVERITY {Warning} [get_drc_checks GTYCHK-2] set_property PACKAGE_PIN C5 [get_ports "NXP_SD1_RX0_N_C"] ;# Bank 232 - MGTYTXN0_232 set_property PACKAGE_PIN C6 [get_ports "NXP_SD1_RX0_P_C"] ;# Bank 232 - MGTYTXP0_232 set_property PACKAGE_PIN D3 [get_ports "NXP_SD1_TX0_N_C"] ;# Bank 232 - MGTYRXN0_232 set_property PACKAGE_PIN D4 [get_ports "NXP_SD1_TX0_P_C"] ;# Bank 232 - MGTYRXP0_232 ################################################################################################################################################################## # # GTY Lanes Connected from FPGA to ARM SOC # ################################################################################################################################################################## set_property PACKAGE_PIN AD3 [get_ports "NXP_SD2_RX0_N"] ;# Bank 228 - MGTYTXN0_228 set_property PACKAGE_PIN AD4 [get_ports "NXP_SD2_RX0_P"] ;# Bank 228 - MGTYTXP0_228 set_property PACKAGE_PIN AC5 [get_ports "NXP_SD2_RX1_N"] ;# Bank 228 - MGTYTXN1_228 set_property PACKAGE_PIN AC6 [get_ports "NXP_SD2_RX1_P"] ;# Bank 228 - MGTYTXP1_228 set_property PACKAGE_PIN AB7 [get_ports "NXP_SD2_RX2_N"] ;# Bank 228 - MGTYTXN2_228 set_property PACKAGE_PIN AB8 [get_ports "NXP_SD2_RX2_P"] ;# Bank 228 - MGTYTXP2_228 set_property PACKAGE_PIN AA5 [get_ports "NXP_SD2_RX3_N"] ;# Bank 228 - MGTYTXN3_228 set_property PACKAGE_PIN AA6 [get_ports "NXP_SD2_RX3_P"] ;# Bank 228 - MGTYTXP3_228 set_property PACKAGE_PIN Y7 [get_ports "NXP_SD2_RX4_N"] ;# Bank 229 - MGTYTXN0_229 set_property PACKAGE_PIN Y8 [get_ports "NXP_SD2_RX4_P"] ;# Bank 229 - MGTYTXP0_229 set_property PACKAGE_PIN W5 [get_ports "NXP_SD2_RX5_N"] ;# Bank 229 - MGTYTXN1_229 set_property PACKAGE_PIN W6 [get_ports "NXP_SD2_RX5_P"] ;# Bank 229 - MGTYTXP1_229 set_property PACKAGE_PIN U6 [get_ports "NXP_SD2_RX6_N"] ;# Bank 229 - MGTYTXN2_229 set_property PACKAGE_PIN U7 [get_ports "NXP_SD2_RX6_P"] ;# Bank 229 - MGTYTXP2_229 set_property PACKAGE_PIN R6 [get_ports "NXP_SD2_RX7_N"] ;# Bank 229 - MGTYTXN3_229 set_property PACKAGE_PIN R7 [get_ports "NXP_SD2_RX7_P"] ;# Bank 229 - MGTYTXP3_229 set_property PACKAGE_PIN AE1 [get_ports "NXP_SD2_TX0_N"] ;# Bank 228 - MGTYRXN0_228 set_property PACKAGE_PIN AE2 [get_ports "NXP_SD2_TX0_P"] ;# Bank 228 - MGTYRXP0_228 set_property PACKAGE_PIN AC1 [get_ports "NXP_SD2_TX1_N"] ;# Bank 228 - MGTYRXN1_228 set_property PACKAGE_PIN AC2 [get_ports "NXP_SD2_TX1_P"] ;# Bank 228 - MGTYRXP1_228 set_property PACKAGE_PIN AB3 [get_ports "NXP_SD2_TX2_N"] ;# Bank 228 - MGTYRXN2_228 set_property PACKAGE_PIN AB4 [get_ports "NXP_SD2_TX2_P"] ;# Bank 228 - MGTYRXP2_228 set_property PACKAGE_PIN AA1 [get_ports "NXP_SD2_TX3_N"] ;# Bank 228 - MGTYRXN3_228 set_property PACKAGE_PIN AA2 [get_ports "NXP_SD2_TX3_P"] ;# Bank 228 - MGTYRXP3_228 set_property PACKAGE_PIN Y3 [get_ports "NXP_SD2_TX4_N"] ;# Bank 229 - MGTYRXN0_229 set_property PACKAGE_PIN Y4 [get_ports "NXP_SD2_TX4_P"] ;# Bank 229 - MGTYRXP0_229 set_property PACKAGE_PIN W1 [get_ports "NXP_SD2_TX5_N"] ;# Bank 229 - MGTYRXN1_229 set_property PACKAGE_PIN W2 [get_ports "NXP_SD2_TX5_P"] ;# Bank 229 - MGTYRXP1_229 set_property PACKAGE_PIN V3 [get_ports "NXP_SD2_TX6_N"] ;# Bank 229 - MGTYRXN2_229 set_property PACKAGE_PIN V4 [get_ports "NXP_SD2_TX6_P"] ;# Bank 229 - MGTYRXP2_229 set_property PACKAGE_PIN U1 [get_ports "NXP_SD2_TX7_N"] ;# Bank 229 - MGTYRXN3_229 set_property PACKAGE_PIN U2 [get_ports "NXP_SD2_TX7_P"] ;# Bank 229 - MGTYRXP3_229 ################################################################################################################################################################## # # GTY Lanes Connected to PCIe Edge Fingers # ################################################################################################################################################################## set_property PACKAGE_PIN AF3 [get_ports "PEX_RX0_N"] ;# Bank 227 - MGTYRXN3_227 set_property PACKAGE_PIN AF4 [get_ports "PEX_RX0_P"] ;# Bank 227 - MGTYRXP3_227 set_property PACKAGE_PIN AT7 [get_ports "PEX_RX10_N"] ;# Bank 225 - MGTYRXN1_225 set_property PACKAGE_PIN AT8 [get_ports "PEX_RX10_P"] ;# Bank 225 - MGTYRXP1_225 set_property PACKAGE_PIN AU9 [get_ports "PEX_RX11_N"] ;# Bank 225 - MGTYRXN0_225 set_property PACKAGE_PIN AU10 [get_ports "PEX_RX11_P"] ;# Bank 225 - MGTYRXP0_225 set_property PACKAGE_PIN AU13 [get_ports "PEX_RX12_N"] ;# Bank 224 - MGTYRXN3_224 set_property PACKAGE_PIN AU14 [get_ports "PEX_RX12_P"] ;# Bank 224 - MGTYRXP3_224 set_property PACKAGE_PIN AT15 [get_ports "PEX_RX13_N"] ;# Bank 224 - MGTYRXN2_224 set_property PACKAGE_PIN AT16 [get_ports "PEX_RX13_P"] ;# Bank 224 - MGTYRXP2_224 set_property PACKAGE_PIN AU17 [get_ports "PEX_RX14_N"] ;# Bank 224 - MGTYRXN1_224 set_property PACKAGE_PIN AU18 [get_ports "PEX_RX14_P"] ;# Bank 224 - MGTYRXP1_224 set_property PACKAGE_PIN AU21 [get_ports "PEX_RX15_N"] ;# Bank 224 - MGTYRXN0_224 set_property PACKAGE_PIN AU22 [get_ports "PEX_RX15_P"] ;# Bank 224 - MGTYRXP0_224 set_property PACKAGE_PIN AG1 [get_ports "PEX_RX1_N"] ;# Bank 227 - MGTYRXN2_227 set_property PACKAGE_PIN AG2 [get_ports "PEX_RX1_P"] ;# Bank 227 - MGTYRXP2_227 set_property PACKAGE_PIN AJ1 [get_ports "PEX_RX2_N"] ;# Bank 227 - MGTYRXN1_227 set_property PACKAGE_PIN AJ2 [get_ports "PEX_RX2_P"] ;# Bank 227 - MGTYRXP1_227 set_property PACKAGE_PIN AK3 [get_ports "PEX_RX3_N"] ;# Bank 227 - MGTYRXN0_227 set_property PACKAGE_PIN AK4 [get_ports "PEX_RX3_P"] ;# Bank 227 - MGTYRXP0_227 set_property PACKAGE_PIN AL1 [get_ports "PEX_RX4_N"] ;# Bank 226 - MGTYRXN3_226 set_property PACKAGE_PIN AL2 [get_ports "PEX_RX4_P"] ;# Bank 226 - MGTYRXP3_226 set_property PACKAGE_PIN AM3 [get_ports "PEX_RX5_N"] ;# Bank 226 - MGTYRXN2_226 set_property PACKAGE_PIN AM4 [get_ports "PEX_RX5_P"] ;# Bank 226 - MGTYRXP2_226 set_property PACKAGE_PIN AN1 [get_ports "PEX_RX6_N"] ;# Bank 226 - MGTYRXN1_226 set_property PACKAGE_PIN AN2 [get_ports "PEX_RX6_P"] ;# Bank 226 - MGTYRXP1_226 set_property PACKAGE_PIN AR1 [get_ports "PEX_RX7_N"] ;# Bank 226 - MGTYRXN0_226 set_property PACKAGE_PIN AR2 [get_ports "PEX_RX7_P"] ;# Bank 226 - MGTYRXP0_226 set_property PACKAGE_PIN AT3 [get_ports "PEX_RX8_N"] ;# Bank 225 - MGTYRXN3_225 set_property PACKAGE_PIN AT4 [get_ports "PEX_RX8_P"] ;# Bank 225 - MGTYRXP3_225 set_property PACKAGE_PIN AU5 [get_ports "PEX_RX9_N"] ;# Bank 225 - MGTYRXN2_225 set_property PACKAGE_PIN AU6 [get_ports "PEX_RX9_P"] ;# Bank 225 - MGTYRXP2_225 set_property PACKAGE_PIN AD7 [get_ports "PEX_TX0_N"] ;# Bank 227 - MGTYTXN3_227 set_property PACKAGE_PIN AD8 [get_ports "PEX_TX0_P"] ;# Bank 227 - MGTYTXP3_227 set_property PACKAGE_PIN AR9 [get_ports "PEX_TX10_N"] ;# Bank 225 - MGTYTXN1_225 set_property PACKAGE_PIN AR10 [get_ports "PEX_TX10_P"] ;# Bank 225 - MGTYTXP1_225 set_property PACKAGE_PIN AT11 [get_ports "PEX_TX11_N"] ;# Bank 225 - MGTYTXN0_225 set_property PACKAGE_PIN AT12 [get_ports "PEX_TX11_P"] ;# Bank 225 - MGTYTXP0_225 set_property PACKAGE_PIN AR13 [get_ports "PEX_TX12_N"] ;# Bank 224 - MGTYTXN3_224 set_property PACKAGE_PIN AR14 [get_ports "PEX_TX12_P"] ;# Bank 224 - MGTYTXP3_224 set_property PACKAGE_PIN AR17 [get_ports "PEX_TX13_N"] ;# Bank 224 - MGTYTXN2_224 set_property PACKAGE_PIN AR18 [get_ports "PEX_TX13_P"] ;# Bank 224 - MGTYTXP2_224 set_property PACKAGE_PIN AT19 [get_ports "PEX_TX14_N"] ;# Bank 224 - MGTYTXN1_224 set_property PACKAGE_PIN AT20 [get_ports "PEX_TX14_P"] ;# Bank 224 - MGTYTXP1_224 set_property PACKAGE_PIN AR21 [get_ports "PEX_TX15_N"] ;# Bank 224 - MGTYTXN0_224 set_property PACKAGE_PIN AR22 [get_ports "PEX_TX15_P"] ;# Bank 224 - MGTYTXP0_224 set_property PACKAGE_PIN AE5 [get_ports "PEX_TX1_N"] ;# Bank 227 - MGTYTXN2_227 set_property PACKAGE_PIN AE6 [get_ports "PEX_TX1_P"] ;# Bank 227 - MGTYTXP2_227 set_property PACKAGE_PIN AG5 [get_ports "PEX_TX2_N"] ;# Bank 227 - MGTYTXN1_227 set_property PACKAGE_PIN AG6 [get_ports "PEX_TX2_P"] ;# Bank 227 - MGTYTXP1_227 set_property PACKAGE_PIN AH3 [get_ports "PEX_TX3_N"] ;# Bank 227 - MGTYTXN0_227 set_property PACKAGE_PIN AH4 [get_ports "PEX_TX3_P"] ;# Bank 227 - MGTYTXP0_227 set_property PACKAGE_PIN AJ5 [get_ports "PEX_TX4_N"] ;# Bank 226 - MGTYTXN3_226 set_property PACKAGE_PIN AJ6 [get_ports "PEX_TX4_P"] ;# Bank 226 - MGTYTXP3_226 set_property PACKAGE_PIN AL5 [get_ports "PEX_TX5_N"] ;# Bank 226 - MGTYTXN2_226 set_property PACKAGE_PIN AL6 [get_ports "PEX_TX5_P"] ;# Bank 226 - MGTYTXP2_226 set_property PACKAGE_PIN AN5 [get_ports "PEX_TX6_N"] ;# Bank 226 - MGTYTXN1_226 set_property PACKAGE_PIN AN6 [get_ports "PEX_TX6_P"] ;# Bank 226 - MGTYTXP1_226 set_property PACKAGE_PIN AP3 [get_ports "PEX_TX7_N"] ;# Bank 226 - MGTYTXN0_226 set_property PACKAGE_PIN AP4 [get_ports "PEX_TX7_P"] ;# Bank 226 - MGTYTXP0_226 set_property PACKAGE_PIN AP7 [get_ports "PEX_TX8_N"] ;# Bank 225 - MGTYTXN3_225 set_property PACKAGE_PIN AP8 [get_ports "PEX_TX8_P"] ;# Bank 225 - MGTYTXP3_225 set_property PACKAGE_PIN AR5 [get_ports "PEX_TX9_N"] ;# Bank 225 - MGTYTXN2_225 set_property PACKAGE_PIN AR6 [get_ports "PEX_TX9_P"] ;# Bank 225 - MGTYTXP2_225 ################################################################################################################################################################## # # GTM Lanes Connected to QSFP #0 Connector # ################################################################################################################################################################## set_property PACKAGE_PIN A12 [get_ports "QSFP28_0_RX1_N"] ;# Bank 234 - MGTMRXN0_234 set_property PACKAGE_PIN A13 [get_ports "QSFP28_0_RX1_P"] ;# Bank 234 - MGTMRXP0_234 set_property PACKAGE_PIN A15 [get_ports "QSFP28_0_RX2_N"] ;# Bank 234 - MGTMRXN1_234 set_property PACKAGE_PIN A16 [get_ports "QSFP28_0_RX2_P"] ;# Bank 234 - MGTMRXP1_234 set_property PACKAGE_PIN A6 [get_ports "QSFP28_0_RX3_N"] ;# Bank 233 - MGTMRXN0_233 set_property PACKAGE_PIN A7 [get_ports "QSFP28_0_RX3_P"] ;# Bank 233 - MGTMRXP0_233 set_property PACKAGE_PIN A9 [get_ports "QSFP28_0_RX4_N"] ;# Bank 233 - MGTMRXN1_233 set_property PACKAGE_PIN A10 [get_ports "QSFP28_0_RX4_P"] ;# Bank 233 - MGTMRXP1_233 set_property PACKAGE_PIN C14 [get_ports "QSFP28_0_TX1_N"] ;# Bank 234 - MGTMTXN0_234 set_property PACKAGE_PIN C15 [get_ports "QSFP28_0_TX1_P"] ;# Bank 234 - MGTMTXP0_234 set_property PACKAGE_PIN C17 [get_ports "QSFP28_0_TX2_N"] ;# Bank 234 - MGTMTXN1_234 set_property PACKAGE_PIN C18 [get_ports "QSFP28_0_TX2_P"] ;# Bank 234 - MGTMTXP1_234 set_property PACKAGE_PIN C8 [get_ports "QSFP28_0_TX3_N"] ;# Bank 233 - MGTMTXN0_233 set_property PACKAGE_PIN C9 [get_ports "QSFP28_0_TX3_P"] ;# Bank 233 - MGTMTXP0_233 set_property PACKAGE_PIN C11 [get_ports "QSFP28_0_TX4_N"] ;# Bank 233 - MGTMTXN1_233 set_property PACKAGE_PIN C12 [get_ports "QSFP28_0_TX4_P"] ;# Bank 233 - MGTMTXP1_233 ################################################################################################################################################################## # # GTY Lanes Connected to QSFP #1 Connector # ################################################################################################################################################################## set_property PACKAGE_PIN K3 [get_ports "QSFP28_1_RX1_N"] ;# Bank 231 - MGTYRXN0_231 set_property PACKAGE_PIN K4 [get_ports "QSFP28_1_RX1_P"] ;# Bank 231 - MGTYRXP0_231 set_property PACKAGE_PIN J1 [get_ports "QSFP28_1_RX2_N"] ;# Bank 231 - MGTYRXN1_231 set_property PACKAGE_PIN J2 [get_ports "QSFP28_1_RX2_P"] ;# Bank 231 - MGTYRXP1_231 set_property PACKAGE_PIN G1 [get_ports "QSFP28_1_RX3_N"] ;# Bank 231 - MGTYRXN2_231 set_property PACKAGE_PIN G2 [get_ports "QSFP28_1_RX3_P"] ;# Bank 231 - MGTYRXP2_231 set_property PACKAGE_PIN E1 [get_ports "QSFP28_1_RX4_N"] ;# Bank 231 - MGTYRXN3_231 set_property PACKAGE_PIN E2 [get_ports "QSFP28_1_RX4_P"] ;# Bank 231 - MGTYRXP3_231 set_property PACKAGE_PIN J6 [get_ports "QSFP28_1_TX1_N"] ;# Bank 231 - MGTYTXN0_231 set_property PACKAGE_PIN J7 [get_ports "QSFP28_1_TX1_P"] ;# Bank 231 - MGTYTXP0_231 set_property PACKAGE_PIN H4 [get_ports "QSFP28_1_TX2_N"] ;# Bank 231 - MGTYTXN1_231 set_property PACKAGE_PIN H5 [get_ports "QSFP28_1_TX2_P"] ;# Bank 231 - MGTYTXP1_231 set_property PACKAGE_PIN G6 [get_ports "QSFP28_1_TX3_N"] ;# Bank 231 - MGTYTXN2_231 set_property PACKAGE_PIN G7 [get_ports "QSFP28_1_TX3_P"] ;# Bank 231 - MGTYTXP2_231 set_property PACKAGE_PIN F4 [get_ports "QSFP28_1_TX4_N"] ;# Bank 231 - MGTYTXN3_231 set_property PACKAGE_PIN F5 [get_ports "QSFP28_1_TX4_P"] ;# Bank 231 - MGTYTXP3_231 ################################################################################################################################################################## # # # ################################################################################################################################################################## set_property PACKAGE_PIN AN9 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 224 - MGTREFCLK0N_224 set_property PACKAGE_PIN AN10 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 224 - MGTREFCLK0P_224 set_property PACKAGE_PIN AM7 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 224 - MGTREFCLK1N_224 set_property PACKAGE_PIN AM8 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 224 - MGTREFCLK1P_224 set_property PACKAGE_PIN AJ9 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 226 - MGTREFCLK0N_226 set_property PACKAGE_PIN AJ10 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 226 - MGTREFCLK0P_226 set_property PACKAGE_PIN AG9 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 226 - MGTREFCLK1N_226 set_property PACKAGE_PIN AG10 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 226 - MGTREFCLK1P_226 set_property PACKAGE_PIN AA9 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 228 - MGTREFCLK1N_228 set_property PACKAGE_PIN AA10 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 228 - MGTREFCLK1P_228 set_property PACKAGE_PIN W9 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 229 - MGTREFCLK0N_229 set_property PACKAGE_PIN W10 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 229 - MGTREFCLK0P_229 set_property PACKAGE_PIN U10 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 229 - MGTREFCLK1N_229 set_property PACKAGE_PIN U11 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 229 - MGTREFCLK1P_229 set_property PACKAGE_PIN T8 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 230 - MGTREFCLK0N_230 set_property PACKAGE_PIN T9 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 230 - MGTREFCLK0P_230 set_property PACKAGE_PIN R10 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 230 - MGTREFCLK1N_230 set_property PACKAGE_PIN R11 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 230 - MGTREFCLK1P_230 set_property PACKAGE_PIN N10 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 231 - MGTREFCLK1N_231 set_property PACKAGE_PIN N11 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 231 - MGTREFCLK1P_231 set_property PACKAGE_PIN M8 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 232 - MGTREFCLK0N_232 set_property PACKAGE_PIN M9 [get_ports "CDSDefaultInput_2p5v"] ;# Bank 232 - MGTREFCLK0P_232 set_property PACKAGE_PIN P4 [get_ports "CDSDefaultOutput_2p5v"] ;# Bank 230 - MGTYTXN0_230 set_property PACKAGE_PIN N6 [get_ports "CDSDefaultOutput_2p5v"] ;# Bank 230 - MGTYTXN1_230 set_property PACKAGE_PIN M4 [get_ports "CDSDefaultOutput_2p5v"] ;# Bank 230 - MGTYTXN2_230 set_property PACKAGE_PIN L6 [get_ports "CDSDefaultOutput_2p5v"] ;# Bank 230 - MGTYTXN3_230 set_property PACKAGE_PIN P5 [get_ports "CDSDefaultOutput_2p5v"] ;# Bank 230 - MGTYTXP0_230 set_property PACKAGE_PIN N7 [get_ports "CDSDefaultOutput_2p5v"] ;# Bank 230 - MGTYTXP1_230 set_property PACKAGE_PIN M5 [get_ports "CDSDefaultOutput_2p5v"] ;# Bank 230 - MGTYTXP2_230 set_property PACKAGE_PIN L7 [get_ports "CDSDefaultOutput_2p5v"] ;# Bank 230 - MGTYTXP3_230 set_property PACKAGE_PIN B3 [get_ports "CDSDefaultOutput_2p5v"] ;# Bank 232 - MGTYTXN1_232 set_property PACKAGE_PIN B4 [get_ports "CDSDefaultOutput_2p5v"] ;# Bank 232 - MGTYTXP1_232 ################################################################################################################################################################## # # # ################################################################################################################################################################## set_property PACKAGE_PIN T3 [get_ports "GND"] ;# Bank 230 - MGTYRXN0_230 set_property PACKAGE_PIN R1 [get_ports "GND"] ;# Bank 230 - MGTYRXN1_230 set_property PACKAGE_PIN N1 [get_ports "GND"] ;# Bank 230 - MGTYRXN2_230 set_property PACKAGE_PIN L1 [get_ports "GND"] ;# Bank 230 - MGTYRXN3_230 set_property PACKAGE_PIN T4 [get_ports "GND"] ;# Bank 230 - MGTYRXP0_230 set_property PACKAGE_PIN R2 [get_ports "GND"] ;# Bank 230 - MGTYRXP1_230 set_property PACKAGE_PIN N2 [get_ports "GND"] ;# Bank 230 - MGTYRXP2_230 set_property PACKAGE_PIN L2 [get_ports "GND"] ;# Bank 230 - MGTYRXP3_230 set_property PACKAGE_PIN C1 [get_ports "GND"] ;# Bank 232 - MGTYRXN1_232 set_property PACKAGE_PIN C2 [get_ports "GND"] ;# Bank 232 - MGTYRXP1_232 ################################################################################################################################################################## # # # ################################################################################################################################################################## set_property PACKAGE_PIN AH8 [get_ports "N45904402"] ;# Bank 225 - MGTRREF_RS set_property PACKAGE_PIN AP31 [get_ports "N53286034"] ;# Bank 66 VCCO - - IO_T0U_N12_VRP_66 set_property IOSTANDARD LVCMOS18 [get_ports "N53286034"] ;# Bank 66 VCCO - - IO_T0U_N12_VRP_66 set_property PACKAGE_PIN AR34 [get_ports "N53286102"] ;# Bank 67 VCCO - - IO_T0U_N12_VRP_67 set_property IOSTANDARD LVCMOS18 [get_ports "N53286102"] ;# Bank 67 VCCO - - IO_T0U_N12_VRP_67 set_property PACKAGE_PIN Y37 [get_ports "N53286147"] ;# Bank 68 VCCO - - IO_T0U_N12_VRP_68 set_property IOSTANDARD LVCMOS18 [get_ports "N53286147"] ;# Bank 68 VCCO - - IO_T0U_N12_VRP_68 set_property PACKAGE_PIN L31 [get_ports "N53286330"] ;# Bank 72 VCCO - - IO_T0U_N12_VRP_72 set_property IOSTANDARD LVCMOS18 [get_ports "N53286330"] ;# Bank 72 VCCO - - IO_T0U_N12_VRP_72 set_property PACKAGE_PIN F25 [get_ports "N53286398"] ;# Bank 73 VCCO - - IO_T0U_N12_VRP_73 set_property IOSTANDARD LVCMOS18 [get_ports "N53286398"] ;# Bank 73 VCCO - - IO_T0U_N12_VRP_73 set_property PACKAGE_PIN E17 [get_ports "N53286443"] ;# Bank 74 VCCO - - IO_T0U_N12_VRP_74 set_property IOSTANDARD LVCMOS18 [get_ports "N53286443"] ;# Bank 74 VCCO - - IO_T0U_N12_VRP_74 set_property PACKAGE_PIN E14 [get_ports "N58613899"] ;# Bank 233 - MGTRREF_RN set_property PACKAGE_PIN AN18 [get_ports "N58659921"] ;# Bank 65 VCCO - 1V8 - IO_L19N_T3L_N1_DBC_AD9N_D11_65 set_property IOSTANDARD LVCMOS18 [get_ports "N58659921"] ;# Bank 65 VCCO - 1V8 - IO_L19N_T3L_N1_DBC_AD9N_D11_65 set_property PACKAGE_PIN AM18 [get_ports "N58659983"] ;# Bank 65 VCCO - 1V8 - IO_L19P_T3L_N0_DBC_AD9P_D10_65 set_property IOSTANDARD LVCMOS18 [get_ports "N58659983"] ;# Bank 65 VCCO - 1V8 - IO_L19P_T3L_N0_DBC_AD9P_D10_65 ################################################################################################################################################################## # # # ################################################################################################################################################################## set_property PACKAGE_PIN E24 [get_ports "No Connect"] ;# Bank 74 VCCO - - IO_L19N_T3L_N1_DBC_AD9N_74 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 74 VCCO - - IO_L19N_T3L_N1_DBC_AD9N_74 set_property PACKAGE_PIN C23 [get_ports "No Connect"] ;# Bank 74 VCCO - - IO_T3U_N12_74 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 74 VCCO - - IO_T3U_N12_74 set_property PACKAGE_PIN D21 [get_ports "No Connect"] ;# Bank 74 VCCO - - IO_T2U_N12_74 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 74 VCCO - - IO_T2U_N12_74 set_property PACKAGE_PIN E19 [get_ports "No Connect"] ;# Bank 74 VCCO - - IO_L13N_T2L_N1_GC_QBC_74 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 74 VCCO - - IO_L13N_T2L_N1_GC_QBC_74 set_property PACKAGE_PIN G23 [get_ports "No Connect"] ;# Bank 74 VCCO - - IO_L7N_T1L_N1_QBC_AD13N_74 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 74 VCCO - - IO_L7N_T1L_N1_QBC_AD13N_74 set_property PACKAGE_PIN G22 [get_ports "No Connect"] ;# Bank 74 VCCO - - IO_T1U_N12_74 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 74 VCCO - - IO_T1U_N12_74 set_property PACKAGE_PIN G14 [get_ports "No Connect"] ;# Bank 74 VCCO - - IO_L1N_T0L_N1_DBC_74 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 74 VCCO - - IO_L1N_T0L_N1_DBC_74 set_property PACKAGE_PIN C29 [get_ports "No Connect"] ;# Bank 73 VCCO - - IO_L19N_T3L_N1_DBC_AD9N_73 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 73 VCCO - - IO_L19N_T3L_N1_DBC_AD9N_73 set_property PACKAGE_PIN C27 [get_ports "No Connect"] ;# Bank 73 VCCO - - IO_T3U_N12_73 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 73 VCCO - - IO_T3U_N12_73 set_property PACKAGE_PIN B31 [get_ports "No Connect"] ;# Bank 73 VCCO - - IO_T2U_N12_73 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 73 VCCO - - IO_T2U_N12_73 set_property PACKAGE_PIN D32 [get_ports "No Connect"] ;# Bank 73 VCCO - - IO_L13N_T2L_N1_GC_QBC_73 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 73 VCCO - - IO_L13N_T2L_N1_GC_QBC_73 set_property PACKAGE_PIN G32 [get_ports "No Connect"] ;# Bank 73 VCCO - - IO_L7N_T1L_N1_QBC_AD13N_73 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 73 VCCO - - IO_L7N_T1L_N1_QBC_AD13N_73 set_property PACKAGE_PIN H29 [get_ports "No Connect"] ;# Bank 73 VCCO - - IO_T1U_N12_73 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 73 VCCO - - IO_T1U_N12_73 set_property PACKAGE_PIN G25 [get_ports "No Connect"] ;# Bank 73 VCCO - - IO_L1N_T0L_N1_DBC_73 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 73 VCCO - - IO_L1N_T0L_N1_DBC_73 set_property PACKAGE_PIN D36 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L19N_T3L_N1_DBC_AD9N_72 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L19N_T3L_N1_DBC_AD9N_72 set_property PACKAGE_PIN C33 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_T3U_N12_72 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_T3U_N12_72 set_property PACKAGE_PIN F34 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L16P_T2U_N6_QBC_AD3P_72 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L16P_T2U_N6_QBC_AD3P_72 set_property PACKAGE_PIN K34 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L12P_T1U_N10_GC_72 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L12P_T1U_N10_GC_72 set_property PACKAGE_PIN J29 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L4N_T0U_N7_DBC_AD7N_72 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L4N_T0U_N7_DBC_AD7N_72 set_property PACKAGE_PIN K33 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L3N_T0L_N5_AD15N_72 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L3N_T0L_N5_AD15N_72 set_property PACKAGE_PIN L33 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L3P_T0L_N4_AD15P_72 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L3P_T0L_N4_AD15P_72 set_property PACKAGE_PIN M33 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L2N_T0L_N3_72 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L2N_T0L_N3_72 set_property PACKAGE_PIN L30 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L1N_T0L_N1_DBC_72 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 72 VCCO - - IO_L1N_T0L_N1_DBC_72 set_property PACKAGE_PIN AA33 [get_ports "No Connect"] ;# Bank 68 VCCO - - IO_L19N_T3L_N1_DBC_AD9N_68 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 68 VCCO - - IO_L19N_T3L_N1_DBC_AD9N_68 set_property PACKAGE_PIN AA30 [get_ports "No Connect"] ;# Bank 68 VCCO - - IO_T3U_N12_68 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 68 VCCO - - IO_T3U_N12_68 set_property PACKAGE_PIN AE29 [get_ports "No Connect"] ;# Bank 68 VCCO - - IO_T2U_N12_68 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 68 VCCO - - IO_T2U_N12_68 set_property PACKAGE_PIN AE33 [get_ports "No Connect"] ;# Bank 68 VCCO - - IO_L13N_T2L_N1_GC_QBC_68 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 68 VCCO - - IO_L13N_T2L_N1_GC_QBC_68 set_property PACKAGE_PIN AD37 [get_ports "No Connect"] ;# Bank 68 VCCO - - IO_L7N_T1L_N1_QBC_AD13N_68 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 68 VCCO - - IO_L7N_T1L_N1_QBC_AD13N_68 set_property PACKAGE_PIN AF35 [get_ports "No Connect"] ;# Bank 68 VCCO - - IO_T1U_N12_68 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 68 VCCO - - IO_T1U_N12_68 set_property PACKAGE_PIN AB37 [get_ports "No Connect"] ;# Bank 68 VCCO - - IO_L1N_T0L_N1_DBC_68 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 68 VCCO - - IO_L1N_T0L_N1_DBC_68 set_property PACKAGE_PIN AJ37 [get_ports "No Connect"] ;# Bank 67 VCCO - - IO_L19N_T3L_N1_DBC_AD9N_67 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 67 VCCO - - IO_L19N_T3L_N1_DBC_AD9N_67 set_property PACKAGE_PIN AH33 [get_ports "No Connect"] ;# Bank 67 VCCO - - IO_T3U_N12_67 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 67 VCCO - - IO_T3U_N12_67 set_property PACKAGE_PIN AK32 [get_ports "No Connect"] ;# Bank 67 VCCO - - IO_T2U_N12_67 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 67 VCCO - - IO_T2U_N12_67 set_property PACKAGE_PIN AM37 [get_ports "No Connect"] ;# Bank 67 VCCO - - IO_L13N_T2L_N1_GC_QBC_67 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 67 VCCO - - IO_L13N_T2L_N1_GC_QBC_67 set_property PACKAGE_PIN AP37 [get_ports "No Connect"] ;# Bank 67 VCCO - - IO_L7N_T1L_N1_QBC_AD13N_67 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 67 VCCO - - IO_L7N_T1L_N1_QBC_AD13N_67 set_property PACKAGE_PIN AP32 [get_ports "No Connect"] ;# Bank 67 VCCO - - IO_T1U_N12_67 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 67 VCCO - - IO_T1U_N12_67 set_property PACKAGE_PIN AU32 [get_ports "No Connect"] ;# Bank 67 VCCO - - IO_L1N_T0L_N1_DBC_67 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 67 VCCO - - IO_L1N_T0L_N1_DBC_67 set_property PACKAGE_PIN AL29 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L19N_T3L_N1_DBC_AD9N_66 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L19N_T3L_N1_DBC_AD9N_66 set_property PACKAGE_PIN AK28 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_T2U_N12_66 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_T2U_N12_66 set_property PACKAGE_PIN AH28 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L18N_T2U_N11_AD2N_66 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L18N_T2U_N11_AD2N_66 set_property PACKAGE_PIN AH27 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L18P_T2U_N10_AD2P_66 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L18P_T2U_N10_AD2P_66 set_property PACKAGE_PIN AK27 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L17N_T2U_N9_AD10N_66 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L17N_T2U_N9_AD10N_66 set_property PACKAGE_PIN AM27 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L15N_T2L_N5_AD11N_66 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L15N_T2L_N5_AD11N_66 set_property PACKAGE_PIN AM26 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L15P_T2L_N4_AD11P_66 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L15P_T2L_N4_AD11P_66 set_property PACKAGE_PIN AM28 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L14N_T2L_N3_GC_66 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L14N_T2L_N3_GC_66 set_property PACKAGE_PIN AL28 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L14P_T2L_N2_GC_66 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 66 VCCO - - IO_L14P_T2L_N2_GC_66 set_property PACKAGE_PIN AH18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L24N_T3U_N11_DOUT_CSO_B_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L24N_T3U_N11_DOUT_CSO_B_65 set_property PACKAGE_PIN AJ16 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L23P_T3U_N8_I2C_SCLK_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L23P_T3U_N8_I2C_SCLK_65 set_property PACKAGE_PIN AM16 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L21N_T3L_N5_AD8N_D07_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L21N_T3L_N5_AD8N_D07_65 set_property PACKAGE_PIN AL16 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L21P_T3L_N4_AD8P_D06_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L21P_T3L_N4_AD8P_D06_65 set_property PACKAGE_PIN AN17 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L20N_T3L_N3_AD1N_D09_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L20N_T3L_N3_AD1N_D09_65 set_property PACKAGE_PIN AK19 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_T2U_N12_CSI_ADV_B_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_T2U_N12_CSI_ADV_B_65 set_property PACKAGE_PIN AN19 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L18P_T2U_N10_AD2P_D12_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L18P_T2U_N10_AD2P_D12_65 set_property PACKAGE_PIN AL20 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L17P_T2U_N8_AD10P_D14_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L17P_T2U_N8_AD10P_D14_65 set_property PACKAGE_PIN AL19 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 set_property PACKAGE_PIN AH20 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L14P_T2L_N2_GC_A04_D20_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L14P_T2L_N2_GC_A04_D20_65 set_property PACKAGE_PIN AM21 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L12N_T1U_N11_GC_A09_D25_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L12N_T1U_N11_GC_A09_D25_65 set_property PACKAGE_PIN AL21 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L12P_T1U_N10_GC_A08_D24_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L12P_T1U_N10_GC_A08_D24_65 set_property PACKAGE_PIN AK22 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 set_property PACKAGE_PIN AJ22 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 set_property PACKAGE_PIN AJ24 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L9N_T1L_N5_AD12N_A15_D31_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L9N_T1L_N5_AD12N_A15_D31_65 set_property PACKAGE_PIN AK24 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L8P_T1L_N2_AD5P_A16_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L8P_T1L_N2_AD5P_A16_65 set_property PACKAGE_PIN AH23 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_T1U_N12_SMBALERT_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_T1U_N12_SMBALERT_65 set_property PACKAGE_PIN AM25 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L6N_T0U_N11_AD6N_A21_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L6N_T0U_N11_AD6N_A21_65 set_property PACKAGE_PIN AL25 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L6P_T0U_N10_AD6P_A20_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L6P_T0U_N10_AD6P_A20_65 set_property PACKAGE_PIN AN22 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L4P_T0U_N6_DBC_AD7P_A24_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L4P_T0U_N6_DBC_AD7P_A24_65 set_property PACKAGE_PIN AP25 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L3N_T0L_N5_AD15N_A27_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L3N_T0L_N5_AD15N_A27_65 set_property PACKAGE_PIN AN25 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L3P_T0L_N4_AD15P_A26_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L3P_T0L_N4_AD15P_A26_65 set_property PACKAGE_PIN AT25 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L1N_T0L_N1_DBC_RS1_65 set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 65 VCCO - 1V8 - IO_L1N_T0L_N1_DBC_RS1_65