Performance and Resource Utilization for Binary Counter v12.0

Vivado Design Suite Release 2021.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbv676 -1 k7_1_128_lut Fabric 128 false 1 UP false 8 CLK 636 160 270 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 631 209 524 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 297 199 337 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_18_lut Fabric 18 false 1 UP false 2 CLK 752 22 29 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 686 22 31 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_47_lut Fabric 47 false 1 UP false 2 CLK 647 25 73 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_48_dsp DSP48 48 false 1 UP false 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 358 8 0 1 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku025 ffva1156 -1 ku_1_128_lut Fabric 128 false 1 UP false 8 CLK 680 177 270 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 642 209 500 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 358 199 311 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_18_lut Fabric 18 false 1 UP false 2 CLK 981 20 29 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 691 22 30 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_47_lut Fabric 47 false 1 UP false 2 CLK 702 25 73 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_48_dsp DSP48 48 false 1 UP false 2 CLK 675 0 0 1 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 631 0 0 1 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 429 8 0 1 0 0 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffva1156 -1 kup_1_128_lut Fabric 128 false 1 UP false 8 CLK 872 176 270 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 872 208 494 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 533 199 355 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1397 20 29 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 1156 22 31 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_47_lut Fabric 47 false 1 UP false 2 CLK 1036 25 73 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 833 0 0 1 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 833 0 0 1 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 625 8 0 1 0 0 PRODUCTION 1.28 02-27-2020

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP ver_1_128_lut Fabric 128 false 1 UP false 8 CLK 680 217 271 0 0 0 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 647 261 495 0 0 0 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 347 271 357 0 0 0 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_18_lut Fabric 18 false 1 UP false 2 CLK 680 19 29 0 0 0 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 680 22 30 0 0 0 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_47_lut Fabric 47 false 1 UP false 2 CLK 680 48 73 0 0 0 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_48_dsp DSP48 48 false 1 UP false 2 CLK 680 0 0 1 0 0 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 680 0 0 1 0 0 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 380 16 0 1 0 0 PRODUCTION 2.01 2021-05-28

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1157 -1 v7_1_128_lut Fabric 128 false 1 UP false 8 CLK 615 160 270 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 610 209 506 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 286 199 277 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_18_lut Fabric 18 false 1 UP false 2 CLK 790 23 29 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 664 22 30 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_47_lut Fabric 47 false 1 UP false 2 CLK 669 25 73 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_48_dsp DSP48 48 false 1 UP false 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 363 8 0 1 0 0 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 -1 vu_1_128_lut Fabric 128 false 1 UP false 8 CLK 653 176 270 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 642 208 500 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 358 199 317 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_18_lut Fabric 18 false 1 UP false 2 CLK 1008 21 29 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 719 22 30 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_47_lut Fabric 47 false 1 UP false 2 CLK 680 25 73 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_48_dsp DSP48 48 false 1 UP false 2 CLK 675 0 0 1 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 631 0 0 1 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 424 8 0 1 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 -1 vup_1_128_lut Fabric 128 false 1 UP false 8 CLK 872 175 270 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 872 208 560 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 538 199 357 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1386 19 29 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 1156 22 30 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_47_lut Fabric 47 false 1 UP false 2 CLK 1047 25 73 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 833 0 0 1 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 833 0 0 1 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 610 8 0 1 0 0 PRODUCTION 1.27 02-28-2020

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1LV zup_1_128_lut Fabric 128 false 1 UP false 8 CLK 636 177 270 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 636 209 494 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 402 199 349 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1030 17 29 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 839 22 30 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_47_lut Fabric 47 false 1 UP false 2 CLK 806 25 73 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 768 0 0 1 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 768 0 0 1 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 461 8 0 1 0 0 PRODUCTION 1.29 08-03-2020

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