Resource Utilization for Clocking Wizard v6.0

Vivado Design Suite Release 2021.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2021.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Kintex-7

Part Information			Configuration Parameters																																																						Resource Utilization
Device	Package	Speed Grade	Configuration Name	PRIMITIVE	USE_FREQ_SYNTH	USE_PHASE_ALIGNMENT	USE_MIN_POWER	USE_DYN_RECONFIG	JITTER_SEL	PRIM_IN_FREQ	IN_JITTER_UNITS	SECONDARY_IN_FREQ	SECONDARY_SOURCE	JITTER_OPTIONS	CLKIN1_UI_JITTER	PRIM_IN_JITTER	SECONDARY_IN_JITTER	CLKIN1_JITTER_PS	CLKIN2_JITTER_PS	CLKOUT1_USED	CLKOUT2_USED	CLKOUT3_USED	CLKOUT4_USED	CLKOUT5_USED	CLKOUT6_USED	CLKOUT7_USED	CLKOUT1_REQUESTED_OUT_FREQ	CLKOUT1_REQUESTED_PHASE	CLKOUT2_REQUESTED_OUT_FREQ	CLKOUT2_REQUESTED_PHASE	CLKOUT3_REQUESTED_OUT_FREQ	CLKOUT3_REQUESTED_PHASE	CLKOUT4_REQUESTED_OUT_FREQ	CLKOUT4_REQUESTED_PHASE	CLKOUT5_REQUESTED_OUT_FREQ	CLKOUT5_REQUESTED_PHASE	CLKOUT6_REQUESTED_OUT_FREQ	CLKOUT6_REQUESTED_PHASE	CLKOUT7_REQUESTED_OUT_FREQ	CLKOUT7_REQUESTED_PHASE	PRIM_SOURCE	CLKOUT1_DRIVES	CLKOUT2_DRIVES	CLKOUT3_DRIVES	CLKOUT4_DRIVES	CLKOUT5_DRIVES	CLKOUT6_DRIVES	CLKOUT7_DRIVES	FEEDBACK_SOURCE	USE_LOCKED	LOCKED_PORT	POWER_DOWN_PORT	RESET_TYPE	INTERFACE_SELECTION	PHASE_DUTY_CONFIG	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k325t	fbg676	2	resource_utils_1	MMCM	true	true	true	true	Max_I_Jitter	391	Units_UI	100.000	Single_ended_clock_capable_pin	PS	870	0.010000	0.000000	236	100	true	true	true	true	true	true	true	156	116	44	170	39	174	39	266	39	155	39	141	36	11	Global_buffer	BUFGCE	BUFGCE	BUFGCE	BUFGCE	BUFGCE	BUFGCE	BUFGCE	FDBK_AUTO_OFFCHIP	true	locked	power_down	ACTIVE_HIGH	Enable_AXI		clk_in1=391 s_axi_aclk=100	3010	1552	8	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	2	resource_utils_2	MMCM	true	true	true	true	Max_I_Jitter	391	Units_UI	100.000	Single_ended_clock_capable_pin	PS	870	0.010000	0.000000	236	100	true	true	true	true	true	true	true	156	116	44	170	39	174	39	266	39	155	39	141	36	11	Global_buffer	BUFGCE	BUFGCE	BUFGCE	BUFGCE	BUFGCE	BUFGCE	BUFGCE	FDBK_AUTO_OFFCHIP	true	locked		ACTIVE_HIGH	Enable_AXI	true	clk_in1=391 s_axi_aclk=100	13484	1572	38	0	0	PRODUCTION 1.12 2017-02-17

COPYRIGHT

Copyright 2021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.