Resource Utilization for MIPI DSI Tx Subsystem v2.2

Vivado Design Suite Release 2021.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2021.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex-7
Zynq UltraScale+

Kintex-7

Part Information			Configuration Parameters					Resource Utilization
Device	Package	Speed Grade	Configuration Name	DSI_LANES	DSI_DATATYPE	DSI_PIXELS	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k325t	ffg900	-2	mipi_config_4	2	RGB565	1	dphy_clk_200M=200 oserdes_clk90_in=400 oserdes_clk_in=400 oserdes_clkdiv_in=125 s_axis_aclk=150 txbyteclkhs_in=125 txclkesc_in=20	2936	2852	0	6	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-2	mipi_config_default_7series	1	RGB888	1	dphy_clk_200M=200 oserdes_clk90_in=400 oserdes_clk_in=400 oserdes_clkdiv_in=125 s_axis_aclk=150 txbyteclkhs_in=125 txclkesc_in=20	2747	2741	0	6	1	PRODUCTION 1.12 2017-02-17

Zynq UltraScale+

Part Information			Configuration Parameters					Resource Utilization
Device	Package	Speed Grade	Configuration Name	DSI_LANES	DSI_DATATYPE	DSI_PIXELS	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	-2	mipi_config_1	2	RGB666_P	2	clkoutphy_in=1000 dphy_clk_200M=200 s_axis_aclk=150 txbyteclkhs_in=125 txclkesc_in=20	3316	3322	0	6	0	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	mipi_config_2	2	RGB666_L	4	clkoutphy_in=1000 dphy_clk_200M=200 s_axis_aclk=150 txbyteclkhs_in=125 txclkesc_in=20	3331	3484	0	6	0	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	mipi_config_3	4	RGB565	1	clkoutphy_in=1000 dphy_clk_200M=200 s_axis_aclk=150 txbyteclkhs_in=125 txclkesc_in=20	3757	3749	0	6	0	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	mipi_config_default	1	RGB888	1	clkoutphy_in=1000 dphy_clk_200M=200 s_axis_aclk=150 txbyteclkhs_in=125 txclkesc_in=20	2993	3055	0	6	0	PRODUCTION 1.29 08-03-2020

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