Performance and Resource Utilization for Reed-Solomon Decoder v9.0

Vivado Design Suite Release 2021.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbv676 1 k7_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 297 1033 931 0 0 2 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 254 1438 1327 0 0 3 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 292 899 799 0 0 2 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 275 1930 1389 0 0 2 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 265 762 801 0 0 2 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 369 924 1556 0 1 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 303 1129 1167 0 1 2 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku025 ffva1156 1 ku_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 385 1027 939 0 0 2 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 358 1438 1343 0 0 3 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 385 899 810 0 0 2 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 374 1941 1404 0 0 2 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 380 764 809 0 0 2 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 429 912 1563 0 1 1 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 369 1111 1170 0 1 2 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffva1156 1 kup_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 560 1128 943 0 0 2 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 1 kup_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 489 1448 1336 0 0 3 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 1 kup_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 511 899 807 0 0 2 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 1 kup_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 544 1932 1401 0 0 2 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 1 kup_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 527 775 801 0 0 2 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 1 kup_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 571 1027 1562 0 1 1 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 1 kup_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 538 1120 1170 0 1 2 PRODUCTION 1.28 02-27-2020

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP ver_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 456 1059 944 0 0 2 PRODUCTION 2.03 2021-08-23
xcvc1902 vsva2197 1LP ver_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 424 1473 1346 0 0 3 PRODUCTION 2.03 2021-08-23
xcvc1902 vsva2197 1LP ver_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 450 983 810 0 0 2 PRODUCTION 2.03 2021-08-23
xcvc1902 vsva2197 1LP ver_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 429 1925 1407 0 0 2 PRODUCTION 2.03 2021-08-23
xcvc1902 vsva2197 1LP ver_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 440 807 816 0 0 2 PRODUCTION 2.03 2021-08-23
xcvc1902 vsva2197 1LP ver_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 505 870 1556 0 1 1 PRODUCTION 2.03 2021-08-23
xcvc1902 vsva2197 1LP ver_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 429 1111 1173 0 1 2 PRODUCTION 2.03 2021-08-23

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1157 1 v7_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 292 1037 931 0 0 2 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 275 1445 1327 0 0 3 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 308 907 807 0 0 2 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 265 1926 1389 0 0 2 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 297 773 802 0 0 2 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 374 927 1556 0 1 1 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 281 1122 1165 0 1 2 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 1 vu_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 380 1027 939 0 0 2 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 363 1437 1343 0 0 3 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 369 896 807 0 0 2 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 385 1952 1401 0 0 2 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 358 756 809 0 0 2 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 440 920 1564 0 1 1 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 374 1114 1166 0 1 2 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 vup_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 533 1034 935 0 0 2 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 1 vup_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 494 1445 1340 0 0 3 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 1 vup_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 533 908 802 0 0 2 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 1 vup_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 549 1995 1401 0 0 2 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 1 vup_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 538 775 809 0 0 2 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 1 vup_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 571 1025 1556 0 1 1 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 1 vup_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 533 1119 1170 0 1 2 PRODUCTION 1.27 02-28-2020

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 1LV zup_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 424 1021 936 0 0 2 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 1LV zup_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 374 1417 1343 0 0 3 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 1LV zup_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 450 909 800 0 0 2 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 1LV zup_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 424 1928 1400 0 0 2 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 1LV zup_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 440 767 809 0 0 2 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 1LV zup_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 456 903 1556 0 1 1 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 1LV zup_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 418 1101 1165 0 1 2 PRODUCTION 1.29 08-03-2020

COPYRIGHT

Copyright 2021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.