Performance and Resource Utilization for TMR Manager v1.0

Vivado Design Suite Release 2021.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2021.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Artix-7
Kintex-7
Kintex UltraScale
Kintex UltraScale+
Spartan-7
Versal ACAP
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Zynq UltraScale+

Artix-7

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_UE_WIDTH	C_NO_OF_COMPARATORS	C_WATCHDOG	C_WATCHDOG_WIDTH	C_SEM_INTERFACE	C_SEM_ASYNC	C_SEM_HEARTBEAT_WATCHDOG	C_SEM_HEARTBEAT_WATCHDOG_WIDTH	C_BRK_DELAY_WIDTH	C_TMR	C_TEST_COMPARATOR	C_STRICT_MISCOMPARE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7a200t	fbg676	-3	Default	3	1	0	30	0	0	0	10	0	1	0	0	none	Clk	540	104	82	0	0	0	PRODUCTION 1.23 2018-06-13

Kintex-7

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_UE_WIDTH	C_NO_OF_COMPARATORS	C_WATCHDOG	C_WATCHDOG_WIDTH	C_SEM_INTERFACE	C_SEM_ASYNC	C_SEM_HEARTBEAT_WATCHDOG	C_SEM_HEARTBEAT_WATCHDOG_WIDTH	C_BRK_DELAY_WIDTH	C_TMR	C_TEST_COMPARATOR	C_STRICT_MISCOMPARE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k325t	ffg900	-3	Default	3	1	0	30	0	0	0	10	0	1	0	0	none	Clk	819	104	82	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-2	Maximum	3	64	1	32	1	0	1	32	32	1	1		Clk=100	N/A	NOT FOUND	561	529	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-2	Minimum	3	1	0	30	0	0	0	10	0	1	0		Clk=100	N/A	NOT FOUND	104	82	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-2	Typical	3	5	1	30	1	0	1	10	16	1	0		Clk=100	N/A	NOT FOUND	339	224	0	0	0	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_UE_WIDTH	C_NO_OF_COMPARATORS	C_WATCHDOG	C_WATCHDOG_WIDTH	C_SEM_INTERFACE	C_SEM_ASYNC	C_SEM_HEARTBEAT_WATCHDOG	C_SEM_HEARTBEAT_WATCHDOG_WIDTH	C_BRK_DELAY_WIDTH	C_TMR	C_TEST_COMPARATOR	C_STRICT_MISCOMPARE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku040	ffva1156	3	Default	3	1	0	30	0	0	0	10	0	1	0	0	none	Clk	1175	104	83	0	0	0	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_UE_WIDTH	C_NO_OF_COMPARATORS	C_WATCHDOG	C_WATCHDOG_WIDTH	C_SEM_INTERFACE	C_SEM_ASYNC	C_SEM_HEARTBEAT_WATCHDOG	C_SEM_HEARTBEAT_WATCHDOG_WIDTH	C_BRK_DELAY_WIDTH	C_TMR	C_TEST_COMPARATOR	C_STRICT_MISCOMPARE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku9p	ffve900	1	Default	3	1	0	30	0	0	0	10	0	1	0	0	none	Clk	1307	103	83	0	0	0	PRODUCTION 1.28 02-27-2020

Spartan-7

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_UE_WIDTH	C_NO_OF_COMPARATORS	C_WATCHDOG	C_WATCHDOG_WIDTH	C_SEM_INTERFACE	C_SEM_ASYNC	C_SEM_HEARTBEAT_WATCHDOG	C_SEM_HEARTBEAT_WATCHDOG_WIDTH	C_BRK_DELAY_WIDTH	C_TMR	C_TEST_COMPARATOR	C_STRICT_MISCOMPARE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7s50	csga324	1	Default	3	1	0	30	0	0	0	10	0	1	0	0	none	Clk	427	103	82	0	0	0	PRODUCTION 1.23 2018-06-13

Versal ACAP

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_UE_WIDTH	C_NO_OF_COMPARATORS	C_WATCHDOG	C_WATCHDOG_WIDTH	C_SEM_INTERFACE	C_SEM_ASYNC	C_SEM_HEARTBEAT_WATCHDOG	C_SEM_HEARTBEAT_WATCHDOG_WIDTH	C_BRK_DELAY_WIDTH	C_TMR	C_TEST_COMPARATOR	C_STRICT_MISCOMPARE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	3HP	Default	3	1	0	30	0	0	0	10	0	1	0	0	none	Clk	1145	104	83	0	0	0	PRODUCTION 2.03 2021-08-23

Virtex-7

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_UE_WIDTH	C_NO_OF_COMPARATORS	C_WATCHDOG	C_WATCHDOG_WIDTH	C_SEM_INTERFACE	C_SEM_ASYNC	C_SEM_HEARTBEAT_WATCHDOG	C_SEM_HEARTBEAT_WATCHDOG_WIDTH	C_BRK_DELAY_WIDTH	C_TMR	C_TEST_COMPARATOR	C_STRICT_MISCOMPARE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1761	-3	Default	3	1	0	30	0	0	0	10	0	1	0	0	none	Clk	769	104	82	0	0	0	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_UE_WIDTH	C_NO_OF_COMPARATORS	C_WATCHDOG	C_WATCHDOG_WIDTH	C_SEM_INTERFACE	C_SEM_ASYNC	C_SEM_HEARTBEAT_WATCHDOG	C_SEM_HEARTBEAT_WATCHDOG_WIDTH	C_BRK_DELAY_WIDTH	C_TMR	C_TEST_COMPARATOR	C_STRICT_MISCOMPARE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu065	ffvc1517	3	Default	3	1	0	30	0	0	0	10	0	1	0	0	none	Clk	1110	104	82	0	0	0	PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_UE_WIDTH	C_NO_OF_COMPARATORS	C_WATCHDOG	C_WATCHDOG_WIDTH	C_SEM_INTERFACE	C_SEM_ASYNC	C_SEM_HEARTBEAT_WATCHDOG	C_SEM_HEARTBEAT_WATCHDOG_WIDTH	C_BRK_DELAY_WIDTH	C_TMR	C_TEST_COMPARATOR	C_STRICT_MISCOMPARE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu3p	ffvc1517	1	Default	3	1	0	30	0	0	0	10	0	1	0	0	none	Clk	1475	104	82	0	0	0	PRODUCTION 1.27 02-28-2020

Zynq UltraScale+

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_UE_WIDTH	C_NO_OF_COMPARATORS	C_WATCHDOG	C_WATCHDOG_WIDTH	C_SEM_INTERFACE	C_SEM_ASYNC	C_SEM_HEARTBEAT_WATCHDOG	C_SEM_HEARTBEAT_WATCHDOG_WIDTH	C_BRK_DELAY_WIDTH	C_TMR	C_TEST_COMPARATOR	C_STRICT_MISCOMPARE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu3eg	sfva625	1	Default	3	1	0	30	0	0	0	10	0	1	0	0	none	Clk	1391	103	82	0	0	0	PRODUCTION 1.29 08-03-2020

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