Resource Utilization for SMPTE UHD-SDI TX SUBSYSTEM v2.0

Vivado Design Suite Release 2021.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2021.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Zynq UltraScale+

Part Information			Configuration Parameters										Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_EXDES_BOARD	C_EXDES_CONFIG	C_VIDEO_INTF	C_LINE_RATE	C_INCLUDE_AXILITE	C_INCLUDE_ADV_FEATURES	C_INCLUDE_EDH	C_PIXELS_PER_CLOCK	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	-2	test_wAXI4SInterface_wAXILITE_wAdvfeature_woEDH_12G_8DS	ZCU106	Pass-through_with_Picxo	AXI4_Stream	12G_SDI_8DS	true	true	false	2	s_axi_aclk=100 sdi_tx_clk=297 video_in_clk=300	4610	9636	0	14	3	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_wAXI4S_waxilite_wADVFEATUR_wEDH_12G_8DS	ZCU106	Pass-through_with_Picxo	AXI4_Stream	12G_SDI_8DS	true	true	true	2	s_axi_aclk=100 sdi_tx_clk=297 video_in_clk=300	4944	10043	0	14	3	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_wNative_SDI_waxilite_woADVFEATUR_woEDH_12G_16DS	ZCU106	Pass-through_with_Picxo	Native_SDI	12G_SDI_16DS	true	false	false	2	s_axi_aclk=100 sdi_tx_clk=297	2998	5953	0	0	0	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_wNative_SDI_waxilite_woADVFEATUR_woEDH_6G	ZCU106	Pass-through_with_Picxo	Native_SDI	6G_SDI	true	false	true	2	s_axi_aclk=100 sdi_tx_clk=149	2361	4752	0	0	0	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_wNative_SDI_woaxilite_woADVFEATUR_woEDH_12G_16DS	ZCU106	Pass-through_with_Picxo	Native_SDI	12G_SDI_16DS	false	false	false	2	sdi_tx_clk=297	2399	2601	0	0	0	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_wNative_SDI_woaxilite_woADVFEATUR_woEDH_6G	ZCU106	Pass-through_with_Picxo	Native_SDI	6G_SDI	false	false	true	2	sdi_tx_clk=149	1838	1987	0	0	0	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_wNative_VIDEO_waxilite_wADVFEATUR_wEDH_6G	ZCU106	Pass-through_with_Picxo	Native_Video	6G_SDI	true	false	false	2	s_axi_aclk=100 sdi_tx_clk=149	3219	6211	0	12	3	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_wNative_VIDEO_woaxilite_wADVFEATUR_wEDH_6G	ZCU106	Pass-through_with_Picxo	Native_Video	6G_SDI	false	false	false	2	sdi_tx_clk=149	2533	3312	0	12	3	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_wNativevideo_waxilite_woADVFEATURE_woEDH_12G_8DS	ZCU106	Pass-through_with_Picxo	Native_Video	12G_SDI_8DS	true	false	false	2	s_axi_aclk=100 sdi_tx_clk=297	3227	6218	0	12	3	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_wNativevideo_woaxilite_woADVFEATURE_woEDH_12G_8DS	ZCU106	Pass-through_with_Picxo	Native_Video	12G_SDI_8DS	false	false	false	2	sdi_tx_clk=297	2542	3318	0	12	3	PRODUCTION 1.29 08-03-2020

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