HLS Pragmas

Optimizations in Vivado HLS

In both SDAccel and SDSoC projects, the hardware kernel must be synthesized from the OpenCL, C, or C++ language, into RTL that can be implemented into the programmable logic of a Xilinx device. Vivado HLS synthesizes the RTL from the OpenCL, C, and C++ language descriptions.

Vivado HLS is intended to work with your SDAccel or SDSoC Development Environment project without interaction. However, Vivado HLS also provides pragmas that can be used to optimize the design: reduce latency, improve throughput performance, and reduce area and device resource utilization of the resulting RTL code. These pragmas can be added directly to the source code for the kernel.

Vivado HLS also provides Tcl set_directive commands that can be passed to the tool at run time to control performance and optimization of the hardware kernel. Those directives are not described here, but are documented in the Vivado Design Suite User Guide: High-Level Synthesis (UG902).

Important: Although the SDSoC environment supports the use of HLS pragmas, the SDSoC compilers automatically define HLS pragmas based on internal processes and hardware requirements. This automatic process is disabled if you manually add HLS pragmas that conflict with the pragmas selected by sdscc/sds++. It is not recommended to specify Vivado HLS pragmas for use with the SDSoC environment, or use set_directive Tcl commands, unless you want to override the automatic selection of HLS pragmas by sdscc or sds++. Refer to "Optimizing the Hardware Function" in the SDSoC Environment Optimization Guide (UG1235) for more information.
The Vivado HLS pragmas include the optimization types specified below:
Table 1. Vivado HLS Pragmas by Type
Type Attributes
Kernel Optimization
Function Inlining
Interface Synthesis
Task-level Pipeline
Pipeline
Loop Unrolling
Loop Optimization
Array Optimization
Structure Packing