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(M10.9.80762.TableTitle.Table.B1.Ports.Added.in.v50) 3833 0 R (M11.9.33324.XAnchorFigure.XRef.Target..Figure.B5) 3842 0 R (M11.9.56237.AppendixTitle.Debugging) 3073 0 R (M12.9.20375.ReferenceCont.6.Vivado.Design.Suite.User.Guide.Designing.with.IP.UG896) 3074 0 R (M12.9.21628.ReferenceCont.8.Vivado.Design.Suite.User.Guide.Programming.and.De) 3732 0 R (M12.9.22109.ReferenceCont.7.Vivado.Design.Suite.User.Guide.Designing.IP.Subsy) 3075 0 R (M12.9.37043.ReferenceCont.9.ISE.to.Vivado.Design.Suite.Migration.Guide.UG911) 3736 0 R (M12.9.42680.Reference.1.IEEE.Standard.80232008.Carrier.Sense.Multiple.Access.with) 3743 0 R (M12.9.55194.ReferenceCont.4.Vivado.Design.Suite.User.Guide.Logic.Simulation.UG900) 3734 0 R (M12.9.58242.ReferenceCont.10.Vivado.Design.Suite.User.Guide.Getting.Started.UG910) 3076 0 R (M12.9.72208.ReferenceCont.2.IEEE.Standard.8021Qbb.Prioritybased.Flow.Control) 3753 0 R (M12.9.74919.ReferenceCont.3.7.Series.Transceivers.User.Guide.UG476) 3077 0 R (M12.9.77315.ReferenceCont.4.UltraScale.Architecture.GTH.Transceivers.User.Guid) 3078 0 R (M12.9.7seriestransug) 3079 0 R (M12.9.98944.ReferenceCont.2.IEEE.Standard.15882008.IEEE.Standard.for.a.Precis) 3756 0 R (M12.9.ieee80232012) 3748 0 R (M12.9.ultratransgthug) 3749 0 R (M12.9.ultratransgtyug) 3080 0 R (M3.9.23701.TableNoteNumberedCont.2.For.the.listed.families.only.a.2.or.faster.speed) 3709 0 R (M3.9.24050.TableNoteNumberedCont.4.GTHE2.transceivers.only) 3081 0 R (M3.9.46217.TableNoteNumberedCont.3.For.the.supported.versions.of.the.tools.see.the.Xilinx.Design) 3082 0 R (M3.9.51550.TableNoteNumberedCont.3.2.2L.or.3) 3624 0 R (M3.9.55626.TableNoteNumbered.1.For.a.complete.list.of.supported.devices.see.Viva) 3705 0 R (M4.9.13380.XAnchorFigure.XRef.Target..Figure.1) 3635 0 R (M4.9.45251.XAnchorFigure.XRef.Target..Figure.12) 3632 0 R (M4.9.48951.Heading1.Unsupported.Features) 3631 0 R (M4.9.55839.XAnchorFigure.XRef.Target..Figure.11) 3083 0 R (M4.9.65101.Heading2.License.Checkers) 3084 0 R (M4.9.73301.XAnchorFigure.XRef.Target..Figure.14) 3633 0 R (M4.9.78952.XAnchorFigure.XRef.Target..Figure.16) 3634 0 R (M4.9.licencechk) 3085 0 R (M5.9.10264.Heading3.MDIO.Register.37.10G.PCS.Control.2) 3086 0 R (M5.9.10392.TableTitle.Table.112.Transceiver.Debug.Signals..UltraScale.Architectur) 3087 0 R (M5.9.11177.TableTitle.Table.650.AN.LP.Base.Page.Ability.Register.1.Bit.Definitions) 3518 0 R (M5.9.11761.TableTitle.Table.657.AN.LP.XNP.Ability.Register.2.Bit.Definitions) 3525 0 R (M5.9.11975.TableTitle.Table.622.10GBASER.FEC.Ability.Register.Bit.Definitions) 3584 0 R (M5.9.12303.Heading3.MDIO.Register.17.10G.PMAPMD.Control.2) 3560 0 R (M5.9.12771.TableTitle.Table.226.PCS.Status.1.Register.Bit.Definition) 3532 0 R (M5.9.13133.TableNoteNumbered.1.This.register.will.be.transferred.automatically.to) 3088 0 R (M5.9.14283.Heading3.MDIO.Register.748.Backplane.Ethernet.Status) 3089 0 R] >> endobj 2631 0 obj << /Limits [(M5.9.14407.Heading3.MDIO.Register.110.10G.PMD.Signal.Receive.OK) (M5.9.40443.TableTitle.Table.524.10GBASER.Status.Register.2.Bit.Definitions)] /Names [(M5.9.14407.Heading3.MDIO.Register.110.10G.PMD.Signal.Receive.OK) 3571 0 R (M5.9.15187.TableTitle.Table.229.10G.PCS.Control.2.Register.Bit.Definitions) 3534 0 R (M5.9.15889.TableTitle.Table.226.Version.Register) 3025 0 R (M5.9.16210.TableTitle.Table.213.10GBASEKR.LP.Coefficient.Update.Register.Bit.Defi) 3577 0 R (M5.9.16270.Heading1.Alignment.and.Synchronization.Status.Ports) 3026 0 R (M5.9.16314.TableTitle.Table.652.AN.XNP.Transmit.Register.0.Bit.Definitions) 3027 0 R (M5.9.16413.TableTitle.Table.627.10GBASER.FEC.Uncorrected.Blocks.Upper.Register.Bit.Definitions) 3028 0 R (M5.9.16902.TableTitle.Table.631.Configuration.Vector..BASER) 3674 0 R (M5.9.16996.TableNoteNumbered.1.This.input.is.4.bits.wide.for.the.GTHE3.transceive) 3489 0 R (M5.9.17042.TableTitle.Table.646.AN.Advertisement.Register.0.Bit.Definitions) 3029 0 R (M5.9.17351.XAnchorFigure.XRef.Target..Figure.23) 3030 0 R (M5.9.19975.TableTitle.Table.25.PMAPMD.Speed.Ability.Register.Bit.Definitions) 3559 0 R (M5.9.20147.Heading3.MDIO.Registers.35.and.36.PCS.Devices.in.Package) 3031 0 R (M5.9.20279.Heading1.Transceiver.Debug.Signals..Zynq7000.Virtex7.a) 3486 0 R (M5.9.21441.TableTitle.Table.632.Configuration.Vector..BASEKR.Specific) 3589 0 R (M5.9.21910.TableNoteNumbered.1.Only.valid.when.the.optional.FEC.block.is.included) 3032 0 R (M5.9.22126.XAnchorFigure.XRef.Target..Figure.21) 3388 0 R (M5.9.23626.TableNoteNumberedCont.2.Reset.controls.for.the.given.registers) 3676 0 R (M5.9.24290.TableNoteNumberedCont.3.Reset.controls.for.the.given.registers) 3033 0 R (M5.9.24617.TableNoteNumberedCont.2.Reset.controls.for.the.given.registers) 3034 0 R (M5.9.25062.TableNoteNumbered.1.saxistxtuser.is.00.when.not.using.1588.it.i) 3596 0 R (M5.9.25438.Heading1.Register.Space) 3392 0 R (M5.9.25457.TableTitle.Table.528.10GBASER.Test.Pattern.Error.Counter.Register.Bit.Definitions) 3496 0 R (M5.9.25726.TableTitle.Table.23.PMAPMD.Control.1.Register.Bit.Definitions) 3617 0 R (M5.9.25965.TableTitle.Table.37.Configuration.signals) 3603 0 R (M5.9.25980.TableNoteNumberedCont.5.If.FEC.Error.Passing.is.enabled.while.FEC.is.enabl) 3591 0 R (M5.9.27051.TableTitle.Table.243.PCS.Speed.Ability.Register.Bit.Definitions) 3035 0 R (M5.9.28338.TableNoteNumbered.1.When.PFC.enabled.txstatisticsvector.has.one.extr) 3036 0 R (M5.9.28434.TableTitle.Table.210.Statistic.Vector.Signals) 3610 0 R (M5.9.28733.XAnchorFigure.XRef.Target..Figure.26) 3037 0 R (M5.9.29365.TableTitle.Table.223.Transmitter.MTU.Configuration.Word) 3467 0 R (M5.9.30344.TableNoteNumbered.1.This.signal.has.no.meaning.or.effect.when.the.core) 3038 0 R (M5.9.30361.TableTitle.Table.230.10G.PCS.Status.2.Register.Bit.Definitions) 3536 0 R (M5.9.30472.Heading3.MDIO.Register.14.PMAPMD.Speed.Ability) 3558 0 R (M5.9.30746.TableTitle.Table.527.10GBASER.Test.Pattern.Control.Register.Bit.Definitions) 3550 0 R (M5.9.30842.TableTitle.Table.649.AN.LP.Base.Page.Ability.Register.0.Bit.Definitions) 3517 0 R (M5.9.31100.TableTitle.Table.616.10GBASEKR.PMD.Control.Register.Bit.Definitions) 3039 0 R (M5.9.31881.Heading3.MDIO.Register.30.PCS.Control.1) 3423 0 R (M5.9.32058.Heading3.Speeding.up.Simulation) 3040 0 R (M5.9.32092.TableTitle.Table.313.Transmit.Statistics.Vector.Bit.Description) 3041 0 R (M5.9.32309.TableNoteNumbered.1.These.reset.signals.should.be.asserted.for.a.single.clock.tick.only) 3675 0 R (M5.9.32886.TableNoteNumberedCont.2.These.registers.will.be.transferred.automatically) 3042 0 R (M5.9.32943.TableTitle.Table.222.Receiver.MTU.Configuration.Word) 3043 0 R (M5.9.33203.XAnchorFigure.XRef.Target..Figure.24) 3482 0 R (M5.9.33614.TableTitle.Table.715.MDIO.Configuration.Word.0) 3474 0 R (M5.9.33687.TableTitle.Table.31.Clientside.interface.ports..transmit) 3044 0 R (M5.9.35363.TableTitle.Table.658.Backplane.Ethernet.Status.Register.Bit.Definitions) 3045 0 R (M5.9.35491.TableNoteNumbered.1.If.FEC.Error.Passing.is.enabled.while.FEC.is.enabl) 3046 0 R (M5.9.35567.TableNoteNumberedCont.2.Only.valid.when.the.optional.AN.block.is.included) 3047 0 R (M5.9.36075.TableNoteNumbered.1.Txxxhis.reset.will.also.reset.all.management.regis) 3048 0 R (M5.9.36089.TableTitle.Table.27.Optical.Module.Interface.Ports) 3475 0 R (M5.9.36260.TableTitle.Table.210.10G.PMD.Signal.Receive.OK.Register.Bit.Definitions) 3572 0 R (M5.9.36333.TableTitle.Table.27.10G.PMAPMD.Control.2.Register.Bit.Definitions) 3049 0 R (M5.9.36434.Heading3.MDIO.Register.725.26.27.AN.LP.XNP.Ability) 3050 0 R (M5.9.37457.TableTitle.Table.645.AN.Status.Register.Bit.Definitions) 3507 0 R (M5.9.37490.XAnchorFigure.XRef.Target..Figure.558) 3595 0 R (M5.9.38087.TableNoteNumbered.1.For.UltraScale.devices.the.DCLK.must.be.freerunni) 3480 0 R (M5.9.38184.TableTitle.Table.619.10GBASEKR.LP.Status.Register.Bit.Definitions) 3051 0 R (M5.9.39094.TableTitle.Table.38.Clock.and.Reset.Ports.Virtex6) 3478 0 R (M5.9.39326.TableTitle.Table.526.10GBASER.Test.Pattern.Seed.B03.Register.Bit.Definitions) 3548 0 R (M5.9.39519.TableNoteNumbered.1.BaseR.Set.from.pmapmdtype.port.BASEKR.retur) 3561 0 R (M5.9.39578.TableNoteNumberedCont.2.Tie.reserved.signals.to.0) 3608 0 R (M5.9.40010.TableTitle.Table.644.AN.Control.Register.Bit.Definitions) 3052 0 R (M5.9.40443.TableTitle.Table.524.10GBASER.Status.Register.2.Bit.Definitions) 3540 0 R] >> endobj 2632 0 obj << /Limits [(M5.9.40486.TableNoteNumbered.1.Cleared.when.read) (M5.9.69925.TableNoteNumberedCont.2.Only.valid.when.the.optional.AN.block.is.included)] /Names [(M5.9.40486.TableNoteNumbered.1.Cleared.when.read) 2996 0 R (M5.9.40576.TableTitle.Table.89.DRP.Interface.Signals) 2997 0 R (M5.9.41471.TableTitle.Table.212.10GBASEKR.PMD.Status.Register.Bit.Definitions) 3575 0 R (M5.9.41540.TableNoteNumbered.1.This.signal.should.be.asserted.for.at.most.3.cycle) 2998 0 R (M5.9.41840.XAnchorFigure.XRef.Target..Figure.610) 3613 0 R (M5.9.42359.TableTitle.Table.29.Clock.and.Reset.Ports..Zynq7000.Virtex7.and.Kintex7De) 3479 0 R (M5.9.43027.TableNoteNumbered.1.These.reset.signals.should.be.asserted.for.a.single.clock.tick.only) 2999 0 R (M5.9.43253.TableNoteNumberedCont.2.When.PFC.enabled.rxconfigurationvector.has.a.bus.width.367) 3000 0 R (M5.9.43264.TableTitle.Table.224.Per.Priority.QuantaRefresh.Register.0x4800x49C) 3001 0 R (M5.9.43738.TableNoteNumbered.1.For.UltraScale.devices.the.DCLK.must.be.freerunni) 3002 0 R (M5.9.44673.Heading1.Register.Space) 5362 0 R (M5.9.44834.Heading3.MDIO.Register.365522.RX.Fixed.Latency.Fractiona) 3003 0 R (M5.9.46183.TableNoteNumbered.1.Latched.when.1174.is.read.Cleared.when.read) 3004 0 R (M5.9.46602.TableTitle.Table.16.Tx.Buffer.BypassManual.Phase.Alignment.Ports) 3005 0 R (M5.9.48327.TableTitle.Table.27.IEEE1588.System.Timer.Ports) 3389 0 R (M5.9.48385.TableTitle.Table.231.10GBASER.Status.Register.1.Bit.Definitions) 3538 0 R (M5.9.48615.TableNoteNumberedCont.2.If.FEC.is.enabled.during.autonegotiation.then.thi) 3006 0 R (M5.9.48888.TableNoteNumberedCont.2.Only.bits.90.are.writable) 3007 0 R (M5.9.49257.TableNoteNumberedCont.2.For.cores.with.optional.AN.block) 3616 0 R (M5.9.49496.TableNoteNumbered.1.All.signals.are.synchronous.to.txclk0) 3351 0 R (M5.9.49926.TableNoteNumberedCont.2.If.FEC.is.enabled.during.autonegotiation.then.thi) 3590 0 R (M5.9.50203.TableTitle.Table.88.DRP.Interface.Ports) 3484 0 R (M5.9.50993.XAnchorFigure.XRef.Target..Figure.557) 3594 0 R (M5.9.51429.TableTitle.Table.311.Training.Interface.Ports..V7K7.FPGAs.BASEKR.only) 3481 0 R (M5.9.51557.TableNoteNumbered.1.This.bit.is.a.constant.and.clock.domain.is.not.app) 3592 0 R (M5.9.51752.TableNoteNumberedCont.2.Tie.reserved.signals.to.0) 3008 0 R (M5.9.51790.TableNoteNumberedCont.4.Toggle.to.load.the.AN.Page.data.from.the.associate) 3009 0 R (M5.9.52018.TableNoteNumberedCont.4.This.bit.is.a.logical.OR.of.two.latching.bits.and) 2975 0 R (M5.9.52191.TableTitle.Table.244.AN.Advertisement.Register.1.Bit.Definitions) 3010 0 R (M5.9.52322.Heading3.MDIO.Register.10.PMAPMD.Control.1) 3011 0 R (M5.9.52629.TableNoteNumbered.1.When.an.optical.module.is.present.the.logical.NOR) 3012 0 R (M5.9.52826.Heading3.MDIO.Register.365520.IEEE1588.Control) 3498 0 R (M5.9.53222.TableTitle.Table.651.AN.LP.Base.Page.Ability.Register.2.Bit.Definitions) 3519 0 R (M5.9.53228.TableNoteNumberedCont.3.The.latter.two.signals.are.required.in.the.core.to) 3485 0 R (M5.9.53388.Heading3.MDIO.Register.71.AN.Status) 3506 0 R (M5.9.53621.TableTitle.Table.714.MDIO.Configuration.Registers) 3473 0 R (M5.9.53627.TableTitle.Table.39.Interrupt.Registers) 3013 0 R (M5.9.54767.TableTitle.Table.3.Configuration.and.Status.Vectors) 3673 0 R (M5.9.54945.TableNoteNumberedCont.2.When.PFC.enabled.rxstatisticsvector.has.one.extr) 3611 0 R (M5.9.55267.TableTitle.Table.634.Status.Vector..BASEKR.Specific) 3014 0 R (M5.9.58115.TableNoteNumbered.1.These.registers.are.programmed.by.writing.to.regis) 3581 0 R (M5.9.59273.TableTitle.Table.26.PMAPMD.Devices.in.Package.Registers.Bit.Definitio) 3015 0 R (M5.9.59629.Heading3.MDIO.Register.31.PCS.Status.1) 3016 0 R (M5.9.59782.TableNoteNumbered.1.This.value.is.different.for.each.1588.permutation) 3500 0 R (M5.9.60708.Heading3.MDIO.Register.332768.VendorSpecific.PCS.Loopbac) 3502 0 R (M5.9.60953.TableTitle.Table.233.10GBASER.Test.Pattern.Seed.A02.Register.Bit.Defi) 3545 0 R (M5.9.61216.TableNoteNumbered.1.All.signals.are.synchronous.to.rxclk0) 3607 0 R (M5.9.62527.TableTitle.Table.26.Signal.Definition) 3670 0 R (M5.9.63112.TableTitle.Table.21.10GBASER.PCSPMA.MDIO.Registers) 3017 0 R (M5.9.63223.TableTitle.Table.633.Status.Vector..BASER) 3018 0 R (M5.9.63895.Heading3.MDIO.Register.1154.10GBASEKR.LD.Coefficient.Upd) 3019 0 R (M5.9.64275.TableTitle.Table.210.Miscellaneous.Signals) 3020 0 R (M5.9.65139.TableTitle.Table.718.MDIO.RX.Data) 3021 0 R (M5.9.65188.TableNoteNumbered.1.Only.bits.30.are.writable) 3501 0 R (M5.9.65613.TableTitle.Table.28.10G.PMAPMD.Status.2.Register.Bit.Definitions) 3562 0 R (M5.9.66065.TableNoteNumbered.1.Writable.only.when.register.11501..0) 3579 0 R (M5.9.66157.TableTitle.Table.216.Receiver.Configuration.Word.0) 3465 0 R (M5.9.67533.TableTitle.Table.624.10GBASER.FEC.Corrected.Blocks.lower.Register.Bit.Definitions) 3587 0 R (M5.9.67673.TableTitle.Table.225.PCS.Control.1.Register.Bit.Definitions) 3022 0 R (M5.9.68421.TableTitle.Table.225.Legacy.Pause.Refresh.Register.0x4A0) 3471 0 R (M5.9.68436.TableTitle.Table.219.Transmitter.Configuration.Word) 3023 0 R (M5.9.68865.ChapterTitle.Product.Specification) 3385 0 R (M5.9.69387.TableTitle.Table.227.Capability.Register) 3024 0 R (M5.9.69925.TableNoteNumberedCont.2.Only.valid.when.the.optional.AN.block.is.included) 3593 0 R] >> endobj 2633 0 obj << /Limits [(M5.9.70016.Heading3.MDIO.Register.1150.10GBASEKR.PMD.Control) (M5.9.97942.TableNoteNumberedCont.3.Typically.constant)] /Names [(M5.9.70016.Heading3.MDIO.Register.1150.10GBASEKR.PMD.Control) 2962 0 R (M5.9.71204.Heading3.MDIO.Register.38.10G.PCS.Status.2) 2963 0 R (M5.9.71227.TableTitle.Table.314.Receive.Statistics.Vector.Description) 2964 0 R (M5.9.71407.Heading3.MDIO.Register.365535.125.ms.Timer.Control..Virtex7Kinte) 3502 0 R (M5.9.71683.TableNoteNumbered.1.When.PFC.enabled.txconfigurationvector.has.a.bus.width.367) 3604 0 R (M5.9.71707.TableTitle.Table.629.Vendorspecific.LD.Training.Register.Bit.Definitions) 2965 0 R (M5.9.71713.TableTitle.Table.32.Clientside.interface.ports..receive) 3597 0 R (M5.9.72371.TableTitle.Table.33.Flow.control.interface.ports) 3598 0 R (M5.9.72856.TableNoteNumberedCont.2.This.bit.is.a.constant.and.clock.domain.is.not.app) 2966 0 R (M5.9.73050.Heading3.MDIO.Register.1171.10GBASER.FEC.Control) 2967 0 R (M5.9.73158.XAnchorFigure.XRef.Target..Figure.611) 3615 0 R (M5.9.73262.TableTitle.Table.24.PMAPMD.Status.1.Register.Bit.Definitions) 2968 0 R (M5.9.73671.Heading1.Resource.Utilization) 3387 0 R (M5.9.73830.Heading3.MDIO.Register.11.PMAPMD.Status.1) 2969 0 R (M5.9.74048.TableTitle.Table.653.AN.XNP.Transmit.Register.1.Bit.Definitions) 3522 0 R (M5.9.74064.TableNoteNumbered.1.Latched.when.1172.is.read.Cleared.when.read) 2970 0 R (M5.9.75197.TableNoteNumberedCont.2.In.fact.this.is.equivalent.to.Training.Done.AND.signal) 2971 0 R (M5.9.75211.TableNoteNumbered.1.This.output.is.8bits.wide.for.the.GTXE2.transceiv) 3488 0 R (M5.9.75423.TableNoteNumbered.1.Cleared.when.read) 3588 0 R (M5.9.75563.TableNoteNumbered.1.Only.valid.when.the.optional.FEC.block.is.included) 2972 0 R (M5.9.76643.TableTitle.Table.213.Transceiver.Debug.Signals) 2973 0 R (M5.9.76820.TableTitle.Table.722.configurationvectorrx.Bit.Definitions) 3605 0 R (M5.9.77225.TableNoteNumbered.1.This.bit.is.equivalent.to.the.FEC.block.lock.if.FE) 2974 0 R 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This subsystem provides a 10-Gigabit Ethernet MAC and a 10-Gigabit Ethernet PCS/PMA in 10GBASE-R and 10GBASE-KR modes to provide an IEEE1588-compatible 10-Gigabit Ethernet port. Acrobat Distiller 10.1.14 (Windows) sub-system, GigE, 10-GB, 10-GigE, 10-Gigabit, Ethernet, Vivado, IP Integrator, IPI, PCS/PMA, XGMAC, IEEE1588, Zynq, Zynq-7000, Virtex, Virtex-7, Kintex, Kintex-7, AXI4-Lite, AXI4-Stream, 10GBASE-R,10BASE-KR, UltraScale+ uuid:116f952c-91cd-4204-8817-8ba8c4eb9add uuid:df3746df-87f8-4d65-9609-c51fae6a59a3 endstream endobj 10042 0 obj << /Author (Xilinx, Inc.) /CreationDate (D:20151103162757Z) /Creator (FrameMaker 10.0.2) /Keywords (sub-system, GigE, 10-GB, 10-GigE, 10-Gigabit, Ethernet, Vivado, IP Integrator, IPI, PCS/PMA, XGMAC, I\ EEE1588, Zynq, Zynq-7000, Virtex, Virtex-7, Kintex, Kintex-7, AXI4-Lite, AXI4-Stream, 10GBASE-R,10BAS\ E-KR, UltraScale+) /ModDate (D:20151103163643Z) /Producer (Xilinx, Inc. via ABCpdf) /Subject (This subsystem provides a 10-Gigabit Ethernet MAC and a 10-Gigabit Ethernet PCS/PMA in 10GBASE-R and \ 10GBASE-KR modes to provide an IEEE1588-compatible 10-Gigabit Ethernet port.) /Title (10 Gigabit Ethernet Subsystem v3.0 Product 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