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(\000T\000D\000L\000_\000X\000i\000l\000i\000n\000x\000.\000j\000o\000b\000o\000p\000t\000i\000o\000\ n\000s)] /Names [(\000T\000D\000L\000_\000X\000i\000l\000i\000n\000x\000.\000j\000o\000b\000o\000p\000t\000i\000o\000\ n\000s) 7038 0 R] >> endobj 7038 0 obj << /EF << /F 1899 0 R >> /F (TDL_Xilinx.joboptions) /Type /Filespec /UF (\000T\000D\000L\000_\000X\000i\000l\000i\000n\000x\000.\000j\000o\000b\000o\000p\000t\000i\000o\000\ n\000s) >> endobj 7039 0 obj << /Length 3023 /Subtype /XML /Type /Metadata >> stream application/pdf AXI 1G/2.5G Ethernet Subsystem v7.0 Product Guide (PG138) Xilinx, Inc. implements a tri-mode (10/100/1000 Mb/s) Ethernet MAC or a 10/100 Mb/s Ethernet MAC. This core supports the use of MII, GMII, SGMII, RGMII, and 1000BASE-X interfaces to connect a MAC to a PHY chip. It also provides on-chip PHY for SGMII and 1000BASE-X modes. 2017-04-07T08:25:16Z FrameMaker 2015.0.5 2017-04-07T08:37:44-07:00 Acrobat Distiller 15.0 (Windows) pg138,ds759,Zynq-7000,Zynq,system-on-chip,SoC,Zynq AP SoC,Virtex-7,Virtex7,Virtex 7,V-7,V7,V 7,Kintex-7,Kintex7,Kintex 7,K-7,K7,K 7,Artix-7,Artix7,Artix 7,A-7,A7,A 7,AXI4-Lite,AXI4-Stream,PHY interfaces,subsystem,Vivado,shared logic,138,1G/2.5G Ethernet, 2.5G Ethernet, UltraScale+,UltraScale uuid:410b15b0-9690-4e2a-ad8a-3e3f457b4633 uuid:929dbb41-d40d-46df-bab7-75eb6524197a 2017-04-07T08:39:56+07:00 endstream endobj 7040 0 obj << /Author (Xilinx, Inc.) /CreationDate (D:20170407082516Z) /Creator (FrameMaker 2015.0.5) /Keywords (pg138,ds759,Zynq-7000,Zynq,system-on-chip,SoC,Zynq AP SoC,Virtex-7,Virtex7,Virtex 7,V-7,V7,V 7,Kintex\ -7,Kintex7,Kintex 7,K-7,K7,K 7,Artix-7,Artix7,Artix 7,A-7,A7,A 7,AXI4-Lite,AXI4-Stream,PHY interfaces\ ,subsystem,Vivado,shared logic,138,1G/2.5G Ethernet, 2.5G Ethernet, UltraScale+,UltraScale) /ModDate (D:20170407083956+07'00') /Producer (Xilinx, Inc. via ABCpdf) /Subject (implements a tri-mode \(10/100/1000 Mb/s\) Ethernet MAC or a 10/100 Mb/s Ethernet MAC. This core supp\ orts the use of MII, GMII, SGMII, RGMII, and 1000BASE-X interfaces to connect a MAC to a PHY chip. It\ also provides on-chip PHY for SGMII and 1000BASE-X modes.) /Title (AXI 1G/2.5G Ethernet Subsystem v7.0 Product Guide \(PG138\)) /XilinxDocID (PG138) >> endobj 7041 0 obj << /Dests 1900 0 R /EmbeddedFiles 7036 0 R /JavaScript 7042 0 R >> endobj 7042 0 obj << /Names [(FrameMaker) 7043 0 R] >> endobj 7043 0 obj << /JS () /S /JavaScript >> endobj 7044 0 obj << /Count 13 /First 7079 0 R /Last 7079 0 R /Type /Outlines >> endobj 7045 0 obj << /Dest (G5.303550) /Next 7154 0 R /Parent 7107 0 R /Prev 7046 0 R /Title (Interrupt Status Register) >> endobj 7046 0 obj << /Dest (G5.303482) /Next 7045 0 R /Parent 7107 0 R /Prev 7047 0 R /Title (MDIO Read Data Register) >> endobj 7047 0 obj << /Dest (G5.303413) /Next 7046 0 R /Parent 7107 0 R /Prev 7048 0 R /Title (MDIO Write Data Register) >> endobj 7048 0 obj << /Dest (G5.457214) /Next 7047 0 R /Parent 7107 0 R /Prev 7049 0 R /Title (MDIO Control Register) >> endobj 7049 0 obj << /Dest (G5.303165) /Next 7048 0 R /Parent 7107 0 R /Prev 7050 0 R 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