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[(\000T\000D\000L\000_\000X\000i\000l\000i\000n\000x\000.\000j\000o\000b\000o\000p\000t\000i\000o\000\ n\000s) (\000T\000D\000L\000_\000X\000i\000l\000i\000n\000x\000.\000j\000o\000b\000o\000p\000t\000i\000o\000\ n\000s)] /Names [(\000T\000D\000L\000_\000X\000i\000l\000i\000n\000x\000.\000j\000o\000b\000o\000p\000t\000i\000o\000\ n\000s) 5934 0 R] >> endobj 5934 0 obj << /EF << /F 1647 0 R >> /F (TDL_Xilinx.joboptions) /Type /Filespec /UF (\000T\000D\000L\000_\000X\000i\000l\000i\000n\000x\000.\000j\000o\000b\000o\000p\000t\000i\000o\000\ n\000s) >> endobj 5935 0 obj << /Length 2920 /Subtype /XML /Type /Metadata >> stream 2021-07-28T12:16:41Z FrameMaker 2019.0.5 application/pdf The core connects the AXI4 interface to SPI slave devices which support the standard, dual or quad SPI protocol. AXI Quad SPI v3.2 LogiCORE IP Product Guide Xilinx, Inc. Acrobat Distiller 15.0 (Windows) PG153,153,Virtex,Kintex,Artix,7 series,IP,AXI,AXI4,AXI4-Lite,SPI,Quad SPI,Virtex-7,Virtex7,Virtex 7,V-7,V7,V 7,Kintex-7,Kintex7,Kintex 7,K-7,K7,K 7,Artix-7,Artix7,Artix 7,A-7,A7,A 7,Vivado,Vivado Design Suite,DS843,UltraScale,843,153,zynq,zynq-7000,ap,all programmable, UltraScale+ 2013-2021 2013-2021 uuid:5f1ef90e-12dd-4d02-99b0-c10f9404eceb uuid:dcc99ae5-23bd-46cb-9b5e-1986da06282c 2021-07-29T18:27:58+05:30 endstream endobj 5936 0 obj << /Author (Xilinx, Inc.) /Copyright (2013-2021) /CreationDate (D:20210728121641Z) /Creator (FrameMaker 2019.0.5) /Keywords (PG153,153,Virtex,Kintex,Artix,7 series,IP,AXI,AXI4,AXI4-Lite,SPI,Quad SPI,Virtex-7,Virtex7,Virtex 7,V\ -7,V7,V 7,Kintex-7,Kintex7,Kintex 7,K-7,K7,K 7,Artix-7,Artix7,Artix 7,A-7,A7,A 7,Vivado,Vivado Design\ Suite,DS843,UltraScale,843,153,zynq,zynq-7000,ap,all programmable, UltraScale+) /ModDate (D:20210729182758+05'30') /PostProcess (v2020.2.0.1) /Producer (Xilinx, Inc. via ABCpdf) /Subject (The core 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