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[(\000T\000D\000L\000_\000j\000o\000b\000o\000p\000t\000i\000o\000n\000s\000_\0001\0002\0001\0000\000\ 1\0005\000.\000j\000o\000b\000o\000p\000t\000i\000o\000n\000s) (\000T\000D\000L\000_\000j\000o\000b\000o\000p\000t\000i\000o\000n\000s\000_\0001\0002\0001\0000\000\ 1\0005\000.\000j\000o\000b\000o\000p\000t\000i\000o\000n\000s)] /Names [(\000T\000D\000L\000_\000j\000o\000b\000o\000p\000t\000i\000o\000n\000s\000_\0001\0002\0001\0000\000\ 1\0005\000.\000j\000o\000b\000o\000p\000t\000i\000o\000n\000s) 14321 0 R] >> endobj 14321 0 obj << /EF << /F 2659 0 R >> /F (TDL_joboptions_121015.joboptions) /Type /Filespec /UF (\000T\000D\000L\000_\000j\000o\000b\000o\000p\000t\000i\000o\000n\000s\000_\0001\0002\0001\0000\000\ 1\0005\000.\000j\000o\000b\000o\000p\000t\000i\000o\000n\000s) >> endobj 14322 0 obj << /Length 2843 /Subtype /XML /Type /Metadata >> stream application/pdf Provides a high performance, low latency 100 Gb/s Ethernet port that allows for a wide range of user customization and statistics gathering. The dedicated block provides both the 100G MAC and PCS logic with support for IEEE 1588-2008 two-step hardware timestamping. UltraScale+ Devices Integrated 100G Ethernet Subsystem v2.2 Product Guide (PG203) Xilinx, Inc. Acrobat Distiller 15.0 (Windows) Virtex UltraScale+,ultrascale+,rs-fec, segmented LBUS, Vivado Design Suite, QuestaSim, XDC, CAUI, IEEE 1588 v2 PTP, IEEE 802.3bd,IEEE 802.3ba,pg165 FrameMaker 2015.0.5 2017-03-24T15:24:24Z uuid:2a0b155c-e1d9-49c6-998f-d1cc7db9e681 uuid:96257b36-7632-479d-94b3-d131b4ec781b 2017-03-24T16:21:44+06:00 endstream endobj 14323 0 obj << /Author (Xilinx, Inc.) /CreationDate (D:20170324152424Z) /Creator (FrameMaker 2015.0.5) /Keywords (Virtex UltraScale+,ultrascale+,rs-fec, segmented LBUS, Vivado Design Suite, QuestaSim, XDC, CAUI, IEE\ E 1588 v2 PTP, IEEE 802.3bd,IEEE 802.3ba,pg165) /ModDate (D:20170324162144+06'00') /Producer (Xilinx, Inc. via ABCpdf) /Subject (Provides a high performance, low latency 100 Gb/s Ethernet port that allows for a wide range of user \ customization and statistics gathering. The dedicated block provides both the 100G MAC and PCS logic \ with support for IEEE 1588-2008 two-step hardware timestamping.) /Title (UltraScale+ Devices Integrated 100G Ethernet Subsystem v2.2 Product Guide \(PG203\)) /XilinxDocID (PG203) >> endobj 14324 0 obj << /Dests 2660 0 R /EmbeddedFiles 14319 0 R >> endobj 14325 0 obj << /Count 16 /First 14345 0 R /Last 14345 0 R /Type /Outlines >> endobj 14326 0 obj << /Dest (G8.388309) /Next 14482 0 R /Parent 14439 0 R /Prev 14483 0 R /Title (QuestaSim) >> endobj xref 0 14327 0000000000 65535 f 0000071368 00000 n 0000071758 00000 n 0000071879 00000 n 0000071999 00000 n 0000072119 00000 n 0000072238 00000 n 0000072358 00000 n 0000072478 00000 n 0000072598 00000 n 0000072718 00000 n 0000072839 00000 n 0000072960 00000 n 0000073081 00000 n 0000073202 00000 n 0000073323 00000 n 0000073475 00000 n 0000073596 00000 n 0000073717 00000 n 0000073838 00000 n 0000073959 00000 n 0000074080 00000 n 0000074201 00000 n 0000074322 00000 n 0000074443 00000 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