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The ChipScope™ Pro IBERT core for 7 Series FPGA GTP transceivers is customizable and designed for evaluating and monitoring GTX tranceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, and access to ports and the dynamic reconfiguration port attributes of the GTX transceivers.
ChipScope, 7 Series, GTP, transevier, IBERT, monitor
The ChipScope™ Pro IBERT core for 7 Series FPGA GTP transceivers is customizable and designed for evaluating and monitoring GTX tranceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, and access to ports and the dynamic reconfiguration port attributes of the GTX transceivers.
2013-03-10T19:07:07.37-07:00
Xilinx, Inc.
ChipScope Integrated Bit Error Ratio Test (IBERT) for 7 Series GTP
2012-07-16T14:38:42-07:00
2010-03-09T01:51:05-08:00
2012-07-16T14:38:42-07:00
FrameMaker 10.0.2
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products:ip-core/chipscope-pro-ibert-for-7-series-gtp
support:document-class/document-type/data-sheets
support:product-type/silicon-devices
applications:ip-functions/fpga-features-and-debug/debug-and-verification
support:product-type/ip-documentation
products:device/fpga/artix-7
22790362de415b060049e80627c90401f1b56a63
2013-03-06T03:39:49.932-08:00
Acrobat Distiller 9.5.1 (Windows)
Xilinx, Inc.
"ChipScope, 7 Series, GTP, transevier, IBERT, monitor"
2011-2012
Acrobat Distiller 9.5.1 (Windows)
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