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The ChipScope™ Pro IBERT core for 7 Series FPGA GTZ transceivers is customizable and designed for evaluating and monitoring GTZ tranceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, and access to ports and the dynamic reconfiguration port attributes of the GTZ transceivers.
ChipScope, 7 Series, GTZ, transevier, IBERT, monitor,Virtex-7,Virtex7,Virtex 7,V-7,V7,V 7,Vivado
The ChipScope™ Pro IBERT core for 7 Series FPGA GTZ transceivers is customizable and designed for evaluating and monitoring GTZ tranceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, and access to ports and the dynamic reconfiguration port attributes of the GTZ transceivers.
2013-03-10T19:07:33.045-07:00
Xilinx, Inc.
Xilinx LogiCORE IP ChipScope Pro Integrated Bit Error Ratio Test (IBERT) for 7 Series GTZ v2.0, Data Sheet
2012-11-09T08:45:32-08:00
2010-03-09T01:51:05-08:00
2012-11-09T08:45:32-08:00
FrameMaker 10.0.2
/content/dam/xilinx/support/documentation/ip_documentation/ibert_7sgtz/v2_0/ds878-ibert-7sgtz.pdf/_jcr_content/renditions/original
support:document-class/document-type/data-sheets
support:product-type/silicon-devices
products:device/fpga/virtex-7
support:product-type/ip-documentation
products:ip-core/chipscope-pro-ibert-for-7-series-gtz
2013-03-06T03:28:50.892-08:00
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Acrobat Distiller 10.1.4 (Windows)
Xilinx, Inc.
"ChipScope, 7 Series, GTZ, transevier, IBERT, monitor,Virtex-7,Virtex7,Virtex 7,V-7,V7,V 7,Vivado"
2011-2012
Acrobat Distiller 10.1.4 (Windows)
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