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Includes pattern generators and checkers implemented in FPGA logic with access to transceiver ports and the dynamic reconfiguration port attributes. IBERT for UltraScale GTH Transceivers v1.2 LogiCORE IP Product Guide (PG173) Xilinx, Inc. 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/Author (Xilinx, Inc.) /CreationDate (D:20150303090640Z) /Creator (FrameMaker 10.0.2) /Keywords (pg173,ChipScope,UltraScale,GTH,transceiver,IBERT,monitor,transever,Kintex-7,K7,K-7,system-on-chip,SoC\ ,Xilinx Platform Studio) /ModDate (D:20150323134015+07'00') /Producer (Xilinx, Inc. via ABCpdf) /Subject (Customizable core designed for evaluating and monitoring GTH transceivers. Includes pattern generator\ s and checkers implemented in FPGA logic with access to transceiver ports and the dynamic reconfigura\ tion port attributes.) /Title (IBERT for UltraScale GTH Transceivers v1.2 LogiCORE IP Product Guide \(PG173\)) /XilinxDocID (PG173) >> endobj 898 0 obj << /Dests 319 0 R >> endobj 899 0 obj << /Count 10 /First 918 0 R /Last 918 0 R /Type /Outlines >> endobj xref 0 900 0000000000 65535 f 0000046165 00000 n 0000046535 00000 n 0000046656 00000 n 0000046776 00000 n 0000046896 00000 n 0000047015 00000 n 0000047135 00000 n 0000047255 00000 n 0000047375 00000 n 0000047495 00000 n 0000047616 00000 n 0000047737 00000 n 0000047858 00000 n 0000047979 00000 n 0000048100 00000 n 0000048221 00000 n 0000048340 00000 n 0000048461 00000 n 0000048582 00000 n 0000048703 00000 n 0000048824 00000 n 0000048943 00000 n 0000049064 00000 n 0000049185 00000 n 0000049306 00000 n 0000049427 00000 n 0000049546 00000 n 0000049696 00000 n 0000049930 00000 n 0000049974 00000 n 0000050051 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