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The Xilinx® UltraScale™ architecture integrated IP core for Interlaken is a scalable chip-to-chip interconnect protocol designed to enable for use in select UltraScale architectures, Acrobat Distiller 10.1.14 (Windows) pg169,Virtex UltraScale,segmented LBUS,LBUS,interconnect protocol,Vivado,Questa SIM,XDC,GTY,GTH,IP catalog,BurstMax,BurstShort,169 uuid:b646bd4a-5bf7-4334-b803-70ba29abd675 uuid:1ddfe1ae-5071-4918-97de-8033f04e2a51 endstream endobj 7159 0 obj << /Author (Xilinx, Inc.) /CreationDate (D:20150928165013Z) /Creator (FrameMaker 10.0.2) /Keywords (pg169,Virtex UltraScale,segmented LBUS,LBUS,interconnect protocol,Vivado,Questa SIM,XDC,GTY,GTH,IP ca\ talog,BurstMax,BurstShort,169) /Language () /ModDate (D:20150929113601+06'00') /Producer (Xilinx, Inc. via ABCpdf) /Subject (The Xilinx UltraScale\222 architecture integrated IP core for Interlaken is a scalable chip-to-chip \ interconnect protocol designed to enable for use in select UltraScale architectures,) /Title (Integrated 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