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1\0005\000.\000j\000o\000b\000o\000p\000t\000i\000o\000n\000s) >> endobj 8291 0 obj << /Length 2844 /Subtype /XML /Type /Metadata >> stream application/pdf The core is a scalable chip-to-chip interconnect protocol designed to enable the following for use in select UltraScale™ and UltraScale+™ architectures. Integrated Interlaken 150G v2.0 LogiCORE IP Product Guide (PG169) Xilinx, Inc. Acrobat Distiller 15.0 (Windows) pg169,Virtex UltraScale,segmented LBUS,LBUS,interconnect protocol,Vivado,Questa SIM,XDC,GTY,GTH,IP catalog,BurstMax,BurstShort,169, Virtex UltraScale, Kintex UltraScale,Virtex UltraScale+, Kintex UltraScale+ FrameMaker 2015.0.5 2016-11-18T05:55:31Z 2016-11-18T07:59:39-08:00 uuid:8c278346-1676-4abb-84a7-028d2e382766 uuid:5e3e089c-4a34-40c9-811a-a140e61ec137 2016-11-18T08:04:17+08:00 endstream endobj 8292 0 obj << /Author (Xilinx, Inc.) /CreationDate (D:20161118055531Z) /Creator (FrameMaker 2015.0.5) /Keywords (pg169,Virtex UltraScale,segmented LBUS,LBUS,interconnect protocol,Vivado,Questa SIM,XDC,GTY,GTH,IP ca\ talog,BurstMax,BurstShort,169, Virtex UltraScale, Kintex UltraScale,Virtex UltraScale+, Kintex UltraS\ cale+) /ModDate (D:20161118080417+08'00') /Producer (Xilinx, Inc. via ABCpdf) /Subject (The core is a scalable chip-to-chip interconnect protocol designed to enable the following for use in\ select UltraScale\222 and UltraScale+\222 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