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UltraScale™ and UltraScale+™ architectures. Integrated Interlaken 150G v2.3 LogiCORE IP Product Guide (PG169) Xilinx, Inc. Acrobat Distiller 15.0 (Windows) pg169,Virtex UltraScale,segmented LBUS,LBUS,interconnect protocol,Vivado,Questa SIM,XDC,GTY,GTH,IP catalog,BurstMax,BurstShort,169, Virtex UltraScale, Kintex UltraScale,Virtex UltraScale+, Kintex UltraScale+,Zynq uuid:d0ee84d6-49d2-4ee4-aec7-26f080232f77 uuid:4b502f27-becd-453d-9dca-25912aa2fdb0 2017-08-24T10:34:00+07:00 endstream endobj 8406 0 obj << /Author (Xilinx, Inc.) /CreationDate (D:20170824045206Z) /Creator (FrameMaker 2015.0.5) /Keywords (pg169,Virtex UltraScale,segmented LBUS,LBUS,interconnect protocol,Vivado,Questa SIM,XDC,GTY,GTH,IP ca\ talog,BurstMax,BurstShort,169, Virtex UltraScale, Kintex UltraScale,Virtex UltraScale+, Kintex UltraS\ cale+,Zynq) /ModDate (D:20170824103400+07'00') /Producer (Xilinx, Inc. via ABCpdf) /Subject (The core is a scalable chip-to-chip interconnect protocol designed to enable the following for use in\ select UltraScale\222 and UltraScale+\222 architectures.) /Title (Integrated Interlaken 150G v2.3 LogiCORE IP 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