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The LogiCORE IP JESD204 core implements a JESD204A or JESD204B interface supporting line rates of 1, 2.5, 3.125 and 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex-6 and Kintex-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. The JESD204 core is a fully-verified solution design delivered via the Xilinx Core Generator software as an NGC netlist. In addition, an example design is provided in Verilog.
Virtex,Kintex,IP,cores,AXI,Kintex-7,Kintex7,Kintex 7,K-7,K7,K 7,Virtex-6,Virtex6,Virtex 6,V-6,V6,V 6,,AXI4,AXI4-Lite,AXI4-Stream,JEDEC,CORE Generator,coregen,duplex, ds814,pg066
The LogiCORE IP JESD204 core implements a JESD204A or JESD204B interface supporting line rates of 1, 2.5, 3.125 and 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex-6 and Kintex-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. The JESD204 core is a fully-verified solution design delivered via the Xilinx Core Generator software as an NGC netlist. In addition, an example design is provided in Verilog.
2013-03-10T19:11:22.043-07:00
Xilinx, Inc.
Xilinx PB011 LogiCORE IP JESD204 v2.2, Product Brief
2012-08-22T08:21:29-07:00
2010-03-09T01:51:05-08:00
2012-08-22T08:21:29-07:00
FrameMaker 10.0.2
/content/dam/xilinx/support/documentation/ip_documentation/jesd204/v2_2/pb011-jesd204.pdf/_jcr_content/renditions/original
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applications:ip-functions/communication-and-networking/serial-interface
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2013-03-06T03:28:18.245-08:00
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Xilinx, Inc.
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