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The LogiCORE IP JESD204 core implements a JESD204A or JESD204B interface supporting line rates of 1, 2.5, 3.125 and 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex-6 and Kintex-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. The JESD204 core is a fully-verified solution design delivered via the Xilinx Core Generator software as an NGC netlist. In addition, an example design is provided in Verilog.
Virtex,Kintex,IP,cores,AXI,Kintex-7,Kintex7,Kintex 7,K-7,K7,K 7,Virtex-6,Virtex6,Virtex 6,V-6,V6,V 6,,AXI4,AXI4-Lite,AXI4-Stream,JEDEC,CORE Generator,coregen,duplex, ds814,pg066
null
"Virtex,Kintex,IP,cores,AXI,Kintex-7,Kintex7,Kintex 7,K-7,K7,K 7,Virtex-6,Virtex6,Virtex 6,V-6,V6,V 6,,AXI4,AXI4-Lite,AXI4-Stream,JEDEC,CORE Generator,coregen,duplex, ds814,pg066"
2013-03-22T16:02:17-07:00
Xilinx, Inc.
Xilinx PB011 LogiCORE IP JESD204 v4.0, Product Brief
2013-03-19T04:20:59-07:00
2010-03-09T01:51:05-08:00
2013-03-19T04:20:59-07:00
c1f4e97b991762d36a36fd967a10988bfe03f926
2013-03-22T16:01:24-07:00
Acrobat Distiller 10.1.5 (Windows)
Xilinx, Inc.
"""Virtex,Kintex,IP,cores,AXI,Kintex-7,Kintex7,Kintex 7,K-7,K7,K 7,Virtex-6,Virtex6,Virtex 6,V-6,V6,V 6,,AXI4,AXI4-Lite,AXI4-Stream,JEDEC,CORE Generator,coregen,duplex, ds814,pg066"""; "The LogiCORE IP JESD204 core implements a JESD204A or JESD204B interface supporting line rates of 1, 2.5, 3.125 and 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex-6 and Kintex-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. The JESD204 core is a fully-verified solution design delivered via the Xilinx Core Generator software as an NGC netlist. In addition, an example design is provided in Verilog."; "Virtex,Kintex,IP,cores,AXI,Kintex-7,Kintex7,Kintex 7,K-7,K7,K 7,Virtex-6,Virtex6,Virtex 6,V-6,V6,V 6,,AXI4,AXI4-Lite,AXI4-Stream,JEDEC,CORE Generator,coregen,duplex, ds814,pg066"
Acrobat Distiller 10.1.5 (Windows)
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