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(unique_82_Connect_42_section_vrq_v2z_xgb) 1424 0 R (unique_82_Connect_42_section_yv2_hfz_xgb) 1432 0 R (unique_82_Connect_42_table_lf3_kcz_xgb) 1413 0 R (unique_82_Connect_42_ul_i3v_vdz_xgb) 1417 0 R (unique_82_Connect_42_ul_wcy_pdz_xgb) 1416 0 R (unique_83) 1312 0 R (unique_83_Connect_42_section_jwk_5jl_snb) 1318 0 R (unique_83_Connect_42_section_typ_xjl_snb) 1315 0 R (unique_83_Connect_42_section_vld_tjl_snb) 1320 0 R (unique_83_Connect_42_ul_on2_2tr_qnb) 1319 0 R (unique_83_Connect_42_ul_q1d_whs_qnb) 1314 0 R (unique_83_Connect_42_ul_vwv_1kl_snb) 1317 0 R (unique_83_Connect_42_ul_y4l_k5r_qnb) 1321 0 R (unique_83_Connect_42_ul_zzz_yfs_qnb) 1316 0 R (unique_84) 1322 0 R (unique_85) 1324 0 R (unique_85_Connect_42_ul_x5h_cbw_pjb) 1326 0 R (unique_86) 1327 0 R (unique_87) 1329 0 R (unique_88) 1331 0 R (unique_88_Connect_42_note_N100C8_N100BA_N100B6_N10019_N10001) 1335 0 R (unique_88_Connect_42_ul_ggp_1sp_1mb) 1336 0 R (unique_88_Connect_42_ul_m5z_b3t_nnb) 1333 0 R (unique_88_Connect_42_ul_zgb_cbh_3gb) 1334 0 R (unique_89) 1337 0 R (unique_89_Connect_42_ul_tnq_wkm_g4b) 1339 0 R (unique_89_Connect_42_ul_tnt_vfm_g4b) 1340 0 R (unique_8_Connect_42_fig_wks_2pc_zlb) 1251 0 R (unique_8_Connect_42_image_qy4_cqc_zlb) 1252 0 R (unique_8_Connect_42_ul_kvt_gm4_ylb) 1250 0 R (unique_9) 1263 0 R (unique_90) 1341 0 R (unique_91) 1346 0 R (unique_92) 1376 0 R (unique_92_Connect_42_fig_tfr_zjk_jhb) 1380 0 R (unique_92_Connect_42_fig_wpf_gwv_tnb) 1382 0 R (unique_92_Connect_42_image_afr_qxv_tnb) 1383 0 R (unique_92_Connect_42_image_qwj_4kk_jhb) 1381 0 R] >> endobj 1479 0 obj << /Limits [(unique_92_Connect_42_note_N100AC_N100A9_N100A1_N1009E_N10096_N10018_N10001) (xSystemMigration)] /Names [(unique_92_Connect_42_note_N100AC_N100A9_N100A1_N1009E_N10096_N10018_N10001) 1386 0 R (unique_92_Connect_42_note_N100C4_N100C1_N100BD_N100BA_N10096_N10018_N10001) 1388 0 R (unique_92_Connect_42_note_N10127_N10100_N100F8_N10018_N10001) 1395 0 R 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(xBootAndConfiguration) 1486 0 R (xBootImageGeneration) 1484 0 R (xDesignFlow) 1482 0 R (xPowerClosure) 1485 0 R (xSystemArchitecture) 1481 0 R (xSystemMigration) 1483 0 R] >> endobj 1480 0 obj << /Author (Xilinx, Inc.) /CreationDate (D:20210629170115-08'00') /Creator (AH XSL Formatter V6.6 MR2 for Linux64 : 6.6.4.36256 \(2018/11/29 19:37JST\)) /Keywords (Versal, methodology, simulation, debug, design flow, boot, configuration, design creation, firmware, \ embedded software, PDI) /ModDate (D:20210629170526+07'00') /PostProcess (v2020.2.0.1) /Producer (Xilinx, Inc. via ABCpdf) /Subject (Provides an overview of Versal\222 ACAP hardware features and block-level considerations when creatin\ g or migrating designs. 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