Additional Resources and Legal Notices

Xilinx Resources

For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support.

Documentation Navigator and Design Hubs

Xilinx® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open DocNav:

  • From the Vivado® IDE, select Help > Documentation and Tutorials.
  • On Windows, select Start > All Programs > Xilinx Design Tools > DocNav.
  • At the Linux command prompt, enter docnav.

Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs:

  • In DocNav, click the Design Hubs View tab.
  • On the Xilinx website, see the Design Hubs page.
Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.

References

These documents provide supplemental material useful with this guide:

  1. Release Notes and Known Issues - https://pages.gitenterprise.xilinx.com/vitis/vitis-ai-staging/master/docs/docs/learn/release_notes.html
  2. Vitis AI Optimizer User Guide (UG1333)
  3. Vitis AI Library User Guide (UG1354)
  4. DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)
  5. DPUCAHX8L for Convolutional Neural Networks Product Guide (PG366)
  6. DPUCAHX8H for Convolutional Neural Network Product Guide (PG367)
  7. DPUCVDX8G for Versal ACAPs Product Guide (PG389)
  8. Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)
  9. Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)
  10. PetaLinux Tools Documentation: Reference Guide (UG1144)

Please Read: Important Legal Notices

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.

AUTOMOTIVE APPLICATIONS DISCLAIMER

AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.

Copyright

© Copyright 2019-2021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, Arm, ARM1176JZ-S, CoreSight, Cortex, PrimeCell, Mali, and MPCore are trademarks of Arm Limited in the EU and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

Section Revision Summary
07/22/2021 Version 1.4
Vitis AI Overview Added Versal AI Core Series: DPUCVDX8G section
TensorFlow 2.x Version (vai_q_tensorflow2) Added vai_q_tensorflow2 Quantization Aware Training, Quantizing with Custom Layers, and vai_q_tensorflow2 Usage sections
PyTorch Version (vai_q_pytorch) Updated vai_q_pytorch QAT
Deploying and Running the Model Updated Apache TVM, Microsoft ONNX Runtime, and TensorFlow Lite
Profiling the Model Added Text Summary

Updated VAI Trace Usage

02/03/2021 Version 1.3
Entire document Updated links
12/17/2020 Version 1.3
Entire document Minor changes
Deep-Learning Processor Unit Added new topics: Alveo U200/U250 Card: DPUCADF8H, Alveo U50/U50LV/U280 Card: DPUCAHX8L, and Versal AI Core Series: DPUCVDX8G.
TensorFlow 2.x Version (vai_q_tensorflow2) Added new section
PyTorch Version (vai_q_pytorch) Added new topics: Module Partial Quantization, vai_q_pytorch Fast Finetuning, and vai_q_pytorch QAT.
Compiling the Model Added new section: Compiling with an XIR-based Toolchain.
Integrating the DPU into Custom Platforms Added new chapter.
VART Programming APIs Added new section: VART APIs.
07/21/2020 Version 1.2
Entire document Minor changes
07/07/2020 Version 1.2
Entire document
  • Added Vitis AI Profiler topic.
  • Added Vitis AI unified API introduction.
DPU Naming Added new topic
Getting Started Updated the chapter
03/23/2020 Version 1.1
DPUCAHX8H Added new topic
Entire document Added contents for Alveo U50 support, U50 DPUV3 enablement, including compiler usage and model deployment description.

PDF Version of Documentation

A PDF of this documentation is available here: Vitis AI User Guide (UG1414).