Simulating an AI Engine Graph Application

The complete set of the AI Engine simulator (aiesimulator) options are described in this section. In most cases, just pointing to pkg-dir is sufficient.

Simulation Input and Output Data Streams

The default bit width for input/output streams is 32 bits. The bit width specifies the number of samples per line on the simulation input file. The interpretation of the samples on each line of the input file is dependent on the data type expected and the PLIO data width. The following table shows how the samples in the input data file are interpreted, depending on the data type and its corresponding PLIO interface specification.

When an application accesses global memory using the GMIO specification (see GMIO Attributes), the simulation needs to model the DDR memory and the routing network connecting the DDR memory to the PL and AI Engines. AI Engine to DDR memory connections are mediated by the DMA data mover that is embedded in the AI Engine array interface and controlled through the GMIO APIs in the PS program. Connections to DDR memory from an AXI4-Stream port on a PL block are mediated by a soft GMIO data mover block, which is generated automatically by the AI Engine compiler for simulation purposes. The data mover converts the streaming interface from the PL blocks to memory-mapped AXI4 interface transactions over the NoC with a specific start address, block size, and burst size as shown in GMIO Attributes.

While simulating with global memory, a memory data file can be supplied using an additional option, --gm-init-file, which initializes the DDR memory with predefined data. This file is a textual byte-dump of the DDR memory starting at a given address. The format of this file is as follows:

<startaddr>:
<byte>
<byte>
…

For example, the AI Engine simulator can be invoked with global memory initialization in the following way:

aiesimulator –-pkg-dir=./Work -–gm-init-file=dump.txt

The simulator also produces an output byte dump for the DDR memory used, in the simulation output directory (default: aiesimulator_output). The name of the output file is based on the internal location of the DDR memory bank (for example, DDRMC_SITE_X1Y0.mem) starting at the base address 0x0. You can use this dump to verify the global memory transactions.

The AI Engine simulator generates an options file that lists the options used for simulating the AI Engine graph application. The options file is automatically generated when the AI Engine simulator is run. This allows reuse of the AI Engine simulator options from the initial graph-level simulation to later in the system-level emulation. You can also manually edit the options file to specify other options as required. The following table lists the options that can be specified in the aiesim_options.txt file, which is located in the aiesimulator_output directory and will only be created if the option, --dump-vcd is used with the aiesimulator command. This file can be specified as part of the command line option to launch the emulator using the launch_hw_emu.sh script as described in Running the System. An example command line follows:

./launch_hw_emu.sh \
-add-env VITIS_LAUNCH_WAVEFORM_BATCH=1 \
-add-env AIE_COMPILER_WORKDIR=${FULL_PATH}/Work \
-aie-sim-options ${FULL_PATH}/aiesimulator_output/aiesim_options.txt

where ${FULL_PATH} must be the full path to the file or directory.

Additionally, you can add more advanced options to log waveform data without having to launch emulation with the Vivado logic simulator (XSIM) GUI. An example command line follows:

./launch_hw_emu.sh \
-user-pre-sim-script pre-sim.tcl

The pre-sim.tcl contains Tcl commands to add waveforms or log design waveforms. For an example see Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393) and for Tcl commands see Vivado Design Suite User Guide: Logic Simulation (UG900).