Vitis Software Platform Release Notes

What's New

For information about what's new in this version of the Vitis™ unified software development platform, see the Vitis What's New Page.

Supported Platforms

Embedded Platforms

Embedded platforms available for use with the Vitis core development kit can be found at the Embedded Platforms download page. Embedded processor platforms such as the Versal VCK190 platform, the Zynq UltraScale+ MPSoC ZCU102/ZCU104 base platform, and the Zynq-7000 base platforms can be optionally used for both the Vitis application acceleration development flow, and the Vitis embedded software development flow. In most cases, however, you can create your own platforms using the Vitis IDE.

Changed Behavior

The following table specifies differences between this release and prior releases that impact behavior or flow when migrating.

Table 1. Changed Behavior Summary
Area	Behavior
Vitis HLS¹	The Git Repository used to be accessible from the left hand lower quadrant. It has moved to the Console area.
	The Analysis perspective no longer exists. The reports and views are now accessible from the Synthesis layout.
	Pragma HLS SHARED was previously a standalone pragma. It is now specified in the `pragma HLS STREAM type=` option. `pragma HLS SHARED` is now `pragma HLS STREAM type=shared`. `pragma HLS SHARED` and `pragma HLS STABLE` now combine to `pragma HLS STREAM type=unsync` (shared and unsynchronized).
	The default setting of `config_interface -m_axi_offset` for the Vivado IP flow has changed to slave. This means that when an `m_axi` interface is added to a Vivado IP an `s_axilite` interface is also added and the offset is managed through it.
	Floating point accumulators and MAC offer new precision for greater control through the `config_op` command. To replicate 2020.2 results in 2021.1, use the following command: `config_op facc -impl auto -precision low`
Vitis profile	In the xrt.ini file, `profile=true` has been changed to `opencl_summary=true` and `opencl_device_counter=true` to capture kernel-side data. These options can be specified separately or together.
Vitis timeline	All trace results (`opencl_trace=true`, `data_transfer_trace=true`, `stall_trace=all`, and others) are added to the are added to the Application Timeline in Vitis analyzer. You can specify which elements are added to the Application Timeline when viewing the report.
Vitis timeline	`timeline_trace` is changed to `opencl_trace`.
Vitis debug	GDB kernel debug during hardware emulation is no longer supported.
Vitis AI Engine	The default optimization level has changed from `xlopt=0` in 2020.2 to `xlopt=1` in 2021.1.
	Using the `-aie-sim-options` of launch_hw_emu.sh, you can profile AI Engines with `AIE_PROFILE` enabled through a text file.
	Changes to `x86simulator`: packet switching construct support, GDB debugging, and `printf()` macros have been added.
	XRT native C++ API for controlling the graph (`xrt::graph`) has been added.
	Hardware Emulation support is now provided for designs accessing GMIO.
	Support for PL kernels in the ADF graph is deprecated.
See the Vitis High-Level Synthesis User Guide (UG1399) for more details.

Known Issues

Known issues for the Vitis software platform are available in AR#76498.