Mapper/Router Methodology

Incorrectly defined user constraints can cause mapper failure. Some of these will be caught by the mapper pre-checker. However, not all of them can be caught in the pre-check phase. In such cases, check for the following conditions.

1. If you have a large number of absolute location or co-location constraints in the graph, check that these constraints do not give conflicting directives to the mapper. This might occur because of the checkerboard nature of the AI Engine array as shown in the following diagram.

   In this diagram, the kernels in red have absolute location constraints while the window buffer (green) between them has a co-location constraint with the first kernel. This will result in mapper failure.

   
   
   

2. If you have absolute location constraints for kernels that are part of a cascade chain, check that these constraints are compatible with the architecture. In AI Engine architecture, the direction of the cascade changes in each row. If you have absolute constraints and cascades as shown in the following diagram, it will cause mapper failure.

   
   
   

3. In some cases the size of the buffers being constrained to a particular tile might exceed the memory capacity of the tile (32 KB in AI Engine architecture). This will result in mapper failure.
4. Each tile in the AI Engine architecture has two input and two output DMA channels. If you have constrained buffers in such a way that a particular tile needs more than this number of DMA channels, it will result in mapper failure.

In some cases, the mapper error might be due to limitations of the tool. In such cases. it might be useful to provide guidance to the tool.

1. Turn off automatic AI Engine compiler floorplanning using the command line switch.

   -–Xmapper=disableFloorplanning

2. Create your own floorplanning by using either bounding box constraints in the graph or areaGroup constraints in the constraints file. This is particularly useful if there are multiple disjoint graphs in the design. Each of these separate graphs can be constrained to a particular region of the array. This technique not only helps design convergence but can also help improve performance by minimizing interference between different graph buffers. The following diagram shows an example using a 16 antenna transmit chain design. The highlighted kernels in blue belong to antenna 4.

   
   
   

   The constraints file syntax to achieve this is as follows.

   {
     "GlobalConstraints": {
       "areaGroup": {
         "name": "ant4_cores",
         "nodeGroup": ["tx_chain4.*"],
         "tileGroup": ["(16,0):(19,3)"]
       }
     }
   }

   The bounding box syntax to achieve this is as follows.

   location<graph>(tx_chain4) = bounding_box(16,0,19,3);

3. Add co-location or absolute location constraints if necessary. If this guidance does not get the design to converge, you can try adding co-location or absolute location constraints. Co-location constraints can be added between kernels and buffers or system memory that you expect to be mapped to the same tile, as shown in the following example.

   location<buffer>(kernel_1.out[0]) = location<kernel>(kernel_1);
   location<stack>(kernel_1) = location<kernel>(kernel_1);

   Absolute location constraints can also be added to certain key kernels or buffers to act as anchors and guide the mapper's placement of other components, as shown in the following example.

   location<kernel>(kernel_1) = tile(20, 0);
   location<buffer>(kernel_1.in[0]) =
   
           { address(19, 0, 0x0),
             address(19, 0, 0x2000) }; // double buffer needs two locations

There are limited switch and DMA FIFOs on the device. When deciding on fifo_depth constraints it is important to consider the amount of FIFOs you specify for an area. This includes taking into account if the nets that have fifo_depth constraints also have area group constraints. In this case make sure that all fifo_depth constraints can be met within the specified area.

If there is a high contention for switch FIFOs, consider moving to DMA FIFOs. Without changing the fifo_depth you can specify the DMA FIFO type using the following constraint.

location<fifo>(net1) = { dma_fifo()}

With careful consideration FIFO locations constraints can be applied, as shown in the following example.

location<fifo>(net2) = { dma_fifo(aie_tile, 15, 0, 0x3100, 32) };
location<fifo>(net3) = { ss_fifo(shim_tile, 16, 0, 0), dma_fifo(aie_tile, 17, 0, 0x3100, 48)}

Sometimes the placement of objects is only considered when defining the area group constraints. This can leave routing without the ability to form all its connections. The following image shows a variety of area group constraints that all allow routing to form connections. In all three of these cases the routing never has to leave the defined area groups to complete its routing.

In contrast there are two common errors with routing and area group constraints. The left side of the following image shows a missing area group for an object. The second case is one where all objects are contained within separate area groups but the two groups are not adjacent. In this case the router has no way to complete the routing of its nets without violating an area group constraint and the router will fail to find a legal solution.

Check PLIO placement to see if it is causing routing congestion. The most common congestion area for router is in the interface tile region. The device has two more incoming/outgoing stream channels for PLIO than the interface tile has connections going into the AI Engine array.

1. If PLIOs are being constrained make sure adequate resources into the AI Engine array are open to handle the locked PLIOs.
2. If possible limit PLIO placement near shadow regions to decrease congestion of routing resources.
3. Check PLIO placement/constraints to verify that crossing such as shown in the following image is not occurring.