Migrating to Vitis HLS

User-Defined and Default Bundle Names

Rule 1: User-specified Bundle Name

IMPORTANT: The Vitis Kernel flow only supports a single s_axilite interface. Creating multiple bundles in this flow, either explicitly or implicitly, will result in an error during synthesis.

This rule explicitly groups all interface ports with the same bundle=<string> into the same AXI4-Lite interface port and names the RTL port the value specified by s_axi_<string>.

void top(char *a, char *b, char *c, char *d) { 
#pragma HLS INTERFACE s_axilite port=a bundle=terry 
#pragma HLS INTERFACE s_axilite port=b bundle=terry 
#pragma HLS INTERFACE s_axilite port=c bundle=stephen 
#pragma HLS INTERFACE s_axilite port=d bundle=jim 
}

INFO: [RTGEN 206-100] Bundling port 'd' to AXI-Lite port jim. 
INFO: [RTGEN 206-100] Bundling port 'c' to AXI-Lite port stephen. 
INFO: [RTGEN 206-100] Bundling port 'a' and 'b' to AXI-Lite port terry. 
INFO: [RTGEN 206-100] Finished creating RTL model for 'example'

Rule 2: Default Bundle Name

This rule explicitly groups all interface ports with no bundle name into the same AXI4-Lite interface port, and uses tool default bundle=<deafult>, and names the RTL port s_axi_<default>.

void top(char *a, char *b, char *c, char *d) { 
#pragma HLS INTERFACE s_axilite port=a 
#pragma HLS INTERFACE s_axilite port=b 
#pragma HLS INTERFACE s_axilite port=c 
#pragma HLS INTERFACE s_axilite port=d 
}

Log fileINFO: [RTGEN 206-100] Bundling port 'a', 'b', 'c' to AXI-Lite port control. 
INFO: [RTGEN 206-100] Finished creating RTL model for 'example'.

Rule 3: Partially Specified Bundle Name

If the bundle names are partially specified, then the tool will create more than one s_axi lite interface port. See the following bundle rules:

• This rule explicitly groups all interface ports with which the bundle name "control" (default name) is specified into the same AXI4-Lite Interface port.
• This rule also explicitly groups all the remaining un-specified bundle names to the new default name which does not conflict with any user names.

void top(char *a, char *b, char *c, char *d) { 
#pragma HLS INTERFACE s_axilite port=a 
#pragma HLS INTERFACE s_axilite port=b 
#pragma HLS INTERFACE s_axilite port=c bundle=control 
#pragma HLS INTERFACE s_axilite port=d bundle=control 
}

INFO: [RTGEN 206-100] Bundling port 'c' and 'd' to AXI-Lite port control. 
INFO: [RTGEN 206-100] Bundling port 'a' and 'b' to AXI-Lite port control_r. 
INFO: [RTGEN 206-100] Finished creating RTL model for 'example'.

• No Global bundle configuration: The default global config option config_interface -m_axi_auto_max_ports false automatically bundles all compatible m_axi interfaces into a single interface, and impacts the bundle rules as follows:
  • Rule 1: User-specified Bundle Name:
  • This rule explicitly groups all interface ports with the same bundle=<string> into a single m_axi interface port and names the RTL port the value specified by m_axi_<string>.

    #pragma HLS INTERFACE m_axi port=a depth=50 bundle=newport
    #pragma HLS INTERFACE m_axi port=b depth=50 bundle=newport
    #pragma HLS INTERFACE m_axi port=c depth=50 bundle=newport
    Log file 
    INFO: [RTGEN 206-500] Setting interface mode on port 'example/newport' to 'm_axi'.
    INFO: [RTGEN 206-500] Setting interface mode on port 'example/newport' to 'm_axi'.
    INFO: [RTGEN 206-500] Setting interface mode on port 'example/newport' to 'm_axi'.
    

    Any ports without the bundle specified are grouped into the default interface gmem0.

    #pragma HLS INTERFACE m_axi port=a depth=50 bundle=newport
    #pragma HLS INTERFACE m_axi port=b depth=50
    #pragma HLS INTERFACE m_axi port=c depth=50
    Log file 
    INFO: [RTGEN 206-500] Setting interface mode on port 'example/newport' to 'm_axi'.
    INFO: [RTGEN 206-500] Setting interface mode on port 'example/gmem0' to 'm_axi'.
    INFO: [RTGEN 206-500] Setting interface mode on port 'example/gmem0' to 'm_axi'.

  • Rule 2: Default Bundle Name:
  • This rule explicitly groups all interface ports with no bundle name specified into a single m_axi interface port and names the port m_axi_gmem0.

    #pragma HLS INTERFACE m_axi port=a depth=50 
    #pragma HLS INTERFACE m_axi port=b depth=50
    #pragma HLS INTERFACE m_axi port=c depth=50 
    Log file 
    INFO: [RTGEN 206-500] Setting interface mode on port 'example/gmem0' to 'm_axi'.
    INFO: [RTGEN 206-500] Setting interface mode on port 'example/gmem0' to 'm_axi'.
    INFO: [RTGEN 206-500] Setting interface mode on port 'example/gmem0' to 'm_axi'.
    

• Global Bundle Configuration: The global config option config_interface -m_axi_auto_max_ports true explicitly maps all m_axi interface ports without a bundle name into individual interface ports and names the RTL port sequentially as m_axi_gmem0, m_axi_gmem1, m_axi_gmem2...

Rule 1: Fully Specified

This rule explicitly groups all the scalar and offsets into the user-specified AXI4-Lite ports.

Rule 2: Default Specified

This rule explicitly groups all the scalar and offsets without offset settings updating the default AXI4-Lite ports.

Rule 3: Partially Specified

If the offsets are partially specified, then the tool will create more than one s_axi lite interface ports.

• Fully Specified Offset: This rule adheres to the user-specified offset settings in the INTERFACE pragma.
• No-offset Specified: If m_axi offset is not specified in the INTERFACE pragma, the global config option: config_interface -m_axi_offset <off/direct/slave> will impact the offset rules.
  • Rule 1: User-specified SAXI Lite: When the INTERFACE pragma specifies an s_axilite interface associated with the m_axi interface, this rule explicitly groups all the m_axi offsets into an AXI4-Lite interface adapter, for which the -m_axi_offset=slave and the -default_slave_interface=s_axilite.

    void top(int *a) {
    #pragma HLS interface mode=m_axi port=a
    #pragma HLS interface mode=s_axilite port=a
    }

  • Rule 2: No SAXI LITE: When the INTERFACE pragma does not associate an s_axilite interface with the m_axi interface, this rule explicitly groups all the m_axi offsets into the tool default offset: -m_axi_offset=slave

    void top(int *a, int *b) {
    #pragma HLS interface mode=m_axi port=a bundle=M0
    #pragma HLS interface mode=m_axi port=b bundle=M0
    }