Revision History
Getting Started with Vitis Revision History
| Section | Revision Summary |
|---|---|
| 10/13/2021 Version 2021.2 | |
| 07/19/2021 Version 2021.1 | |
| N/A | No changes to this section. |
| 06/16/2021 Version 2021.1 | |
| Installation Requirements | Updated to 2021.1. |
| Installing the Vitis Software Platform | Updated to 2021.1. |
| Setting Up the Environment to Run the Vitis Software Platform | Updated to 2021.1. |
| Data Center Application Acceleration Development Flow | Updated Running the Application description and figure. |
| Embedded Processor Application Acceleration Development Flow | Updated Running the Application description and figure. |
| Methodology for Developing C/C++ Kernels | Added description and link to UG1399. |
| About the High-Level Synthesis Compiler | Updated link to UG1399. |
Developing Applications Revision History
| Section | Revision Summary |
|---|---|
| 10/13/2021 Version 2021.2 | |
| 07/19/2021 Version 2021.1 | |
| N/A | No changes to this section. |
| 06/16/2021 Version 2021.1 | |
| Programming Model | Updated section. |
| Device Topology | Updated description to CPU. |
| Kernel Properties | Updated section. |
| Clock and Reset Requirements | Updated table. |
| Command Queues | Added note. |
| Host Programming | Added section. |
| C/C++ Kernels | Updated link. |
| Process Execution Modes | Updated section. |
| Interfaces | Added throughput and link. |
| Dataflow Optimization | Added best practice and link. |
| Streaming Data in User-Managed Never-Ending Kernels | Added with subtopics. |
| Kernel Interface Requirements | Updated section. |
| RTL Kernels | Updated section. |
| Creating User-Managed RTL Kernels | Added with subtopics. |
Building and Running the Application Revision History
| Section | Revision Summary |
|---|---|
| 10/13/2021 Version 2021.2 | |
| 07/19/2021 Version 2021.1 | |
| N/A | No changes to this section. |
| 06/16/2021 Version 2021.1 | |
| Building the Device Binary | Updated to Vivado IP packager. |
| Compiling Kernels with Vitis HLS | Updated description. |
| Assigning Compute Units to SLRs | Added important note. |
| Managing Clock Frequencies | Updated section. |
| Running Multiple Implementation Strategies for Timing Closure | Minor update. |
| Output Directories of the v++ Command | Updated profile_summary.csv and timeline_trace.csv |
| Running Emulation on an Embedded Processor Platform | Updated profile_summary.csv and timeline_trace.csv |
| Working with SystemC Models | Added. |
Profiling, Optimizing, and Debugging the Application Revision History
| Section | Revision Summary |
|---|---|
| 10/13/2021 Version 2021.2 | |
| 07/19/2021 Version 2021.1 | |
| Enabling Kernels for Debugging with Chipscope | Added Important and Tip notes and flattened design description in System ILA. |
| 06/16/2021 Version 2021.1 | |
| Enabling Profiling in Your Application | Updated power_profile. |
| Continuous Trace Capture | Added. |
| Custom Profiling of the Host Application | Updated section. |
| Profiling of C++ Code | Updated user_range code and removed note. |
| Generating and Opening the Profile Summary Report | Updated #2 code and profile_summary. |
| Timeline Trace | Updated title and description. |
| Generating and Opening the Timeline Trace | Updated title and description. |
| Interpreting the Timeline Trace | Updated title and description. |
| Generating and Opening the Waveform Reports | Updated #2 code. |
| Interpreting Data in the Waveform Views | Updated description. |
| Multiple In-Order Command Queues | Added note. |
| GDB-Based Debugging | Removed hardware. |
| GDB Kernel-Based Debugging | Removed hardware. |
| Launching Host and Kernel Debug | Removed hardware. |
| Debugging in Hardware Emulation | Updated figure. |
| GDB-Based Debugging in Hardware Emulation | Removed section. |
| Enable Waveform Debugging with the Vitis Compiler Command | Updated #2 code. |
| Using the Xilinx xbutil Utility | Updated Performance Monitor descriptions. |
| Kernel Hangs Due to AXI Violations | Updated #4 tip note. |
| Example of Command Line Debugging | Updated #8. |
Vitis Environment Reference Materials Revision History
| Section | Revision Summary |
|---|---|
| 10/13/2021 Version 2021.2 | |
| 07/19/2021 Version 2021.1 | |
| N/A | No changes to this section. |
| 06/16/2021 Version 2021.1 | |
| Vitis Compiler General Options | Updated descriptions. |
| --advanced Options | Removed gdb option in table and updated --advanced.param table. |
| --clock Options | Updated section. |
| --connectivity Options | Added --connectivity.connect and re-organized. |
| --hls Options | Added --hls.export_mode. |
| --package Options | Added tip note in --package.boot_mode and updated --package.ps_elf. |
| Vitis Compiler Configuration File | Updated table. |
| launch_emulator Utility | Updated section. |
| package_xo Command | Updated -kernel_files description. |
| RTL Kernel XML File | Updated hwControlProtocol description. |
| xbutil Utility | Added script description. |
| xbmgmt Utility | Added Tip note. |
| xclbinutil Utility | Updated table. |
| xrt.ini File | Updated Debug and Emulation tables. |
Using the Vitis Analyzer Revision History
| Section | Revision Summary |
|---|---|
| 10/13/2021 Version 2021.2 | |
| 07/19/2021 Version 2021.1 | |
| Adding Hardware Interfaces | Added important note to General Requirements. |
| Enabling Hardware Emulation for Extensible XSA | Added important note to #3. |
| Validating an Embedded Platform | Added. |
| 06/16/2021 Version 2021.1 | |
| Configuring the Vitis Analyzer | Updated Run Summary. |
| Diff Two Timeline Trace Reports | Updated figure. |
| Platform and System Diagrams | Updated profile_summary.csv and added Device Map. |
| Link Summary: Multiple Strategies and Timing Reports | Added. |
| Creating an Archive File | Updated profile_summary.csv, timeline_trace.csv, and note. |
Using the Vitis IDE Revision History
| Section | Revision Summary |
|---|---|
| 10/13/2021 Version 2021.2 | |
| 07/19/2021 Version 2021.1 | |
| N/A | No changes to this section. |
| 06/16/2021 Version 2021.1 | |
| Output Directories from the Vitis IDE | Updated profile_summary.csv and timeline_trace.csv |
| vitis -debug Command Line | Updated -kernels. |
| Vitis Binary Container Settings | Updated figure and description. |
| Vitis IDE Debug Flow | Removed hardware and note at the end. |
Using Vitis Embedded Platforms Revision History
| Section | Revision Summary |
|---|---|
| 10/13/2021 Version 2021.2 | |
| 07/19/2021 Version 2021.1 | |
| Platform Types | Minor updates. |
| 06/16/2021 Version 2021.1 | |
| Platform Types | Minor updates. |
| Enabling Hardware Emulation for Extensible XSA | Updated 2b and 2c. |
Additional Information
| Section | Revision Summary |
|---|---|
| 10/13/2021 Version 2021.2 | |
| 07/19/2021 Version 2021.1 | |
| N/A | No changes to this section. |
| 06/16/2021 Version 2021.1 | |
| OpenCL Programming | Added. |
| Understanding an FPGA Architecture | Minor updates. |
| Legacy Reference | Added. |
| Coding Guidelines for Free-Running Kernels | Added Tip note. |