AR# 35118

描述

Read Leveling Stage 1 is the first stage of read calibration performed by the Virtex-6 MIG DDR2/DDR3 design. It is performed after Memory Initialization and Write Leveling (DDR3 only). The purpose of this calibration stage is to center the capture clock in the read data window.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

During Read Leveling Stage 1, a data pattern (FF00FF00FF00FF00) is written to memory and then continuously read back. During the reads, the capture clock is adjusted individually for each DQS group to find the edges of the read data valid window (or the read data eye). All bits of a DQS group are checked simultaneously. The number of edges found is based on frequency varying from 0, 1, or 2 edges. The lower the frequency, the less edges (possibly 0) that can be detected. This is because 32 IDELAY taps exist. With a larger period, the 32 taps can be ran through before an edge is found. The calibration algorithm accounts for this.

After the edge detection, the capture clock phase is adjusted to ensure data capture at the ISERDES takes place in the middle of the data eye. When only one edge is found, the capture clock is offset from that edge by 0.25 * (clock period).

The following picture shows the usage of the capture clock within a DQS group of ISERDES:

Additional Information:

• For detailed information on Read Leveling Stage 1, please see the DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture > PHY section of UG406.
• For information on other calibration stages, please see (Xilinx Answer 34740)
• For information on debugging calibration errors/failures, please see (Xilinx Answer 34743)

链接问答记录

主要问答记录

相关答复记录