The Spartan-6 FPGA DDR2/DDR3 MIG design can be generated with two output designs: the User Design and the Example Design.This section of the MIG Design Assistant focuses on the MIG-generated User Design for Spartan-6 FPGA DDR3/DDR2 designs. Below, you will find information related to your specific question.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.The MIG-generated User Design is the same as the Example Design except that it does not include a synthesizable test bench to generate various traffic data patterns to the memory controller. The User Design is meant to interface to your user logic viathe User Interface.For information on driving the User Interface, please see (Xilinx Answer 44094).
For a complete description on usage of the user design and user interface for Spartan-6 FPGA DDR3/DDR2 designs, pleasesee the Virtex-6 FPGA Memory Interface Solutions User Guide (UG416) and the Spartan-6 FPGA Memory Controller User Guide (UG388).
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 44094 | MIG Spartan-6 FPGA DDR2/DDR3 - How do I drive the user interface? | N/A | N/A |
| 44095 | MIG Spartan-6 FPGA DDR2/DDR3 - MIG Output | N/A | N/A |
| 43595 | MIG Spartan-6 FPGA DDR2/DDR3 - Using CORE Generator | N/A | N/A |
| AR# 44320 | |
|---|---|
| 日期 | 12/15/2012 |
| 状态 | Active |
| Type | 综合文章 |
| 器件 | |
| IP | |