属性 | 值 | Â | Â | Â |
RX_DEBUG_CFG | 12'h000 | Â | Â | Â |
全速: 线速<= 6.6Gbps (RXOUT_DIV=1) | 半速: 线速 1.6 - 6.25Gbps (RXOUT_DIV=2) | 1/4 速: 线速 0.8 - 3.125Gbps (RXOUT_DIV=4) | 1/8 速: 线速 0.5 - 1.5625Gbps (RXOUT_DIV=8) | |
RXCDR_CFG | CDR setting < +/- 200 ppm 72'h03_0000_23FF_1040_0020 CDR setting < +/- 700 ppm 72'h03_8000_23FF_1040_0020 CDR setting < +/- 1250 ppm 72'h03_8000_23FF_1040_0020 | CDR setting < +/- 200 ppm 72'h03_0000_23FF_1020_0020 CDR setting < +/- 700 ppm 72'h03_8000_23FF_1020_0020 CDR setting < +/- 1250 ppm 72'h03_8000_23FF_1020_0020 | CDR setting < +/- 200 ppm 72'h03_0000_23FF_1010_0020 CDR setting < +/- 700 ppm 72'h03_8000_23FF_1010_0020 CDR setting < +/- 1250 ppm 72'h03_8000_23FF_1010_0020 | CDR setting < +/- 200 ppm 72'h03_0000_23FF_1008_0020 CDR setting < +/- 700 ppm 72'h03_8000_23FF_1008_0020 CDR setting < +/- 1250 ppm 72'h03_8000_23FF_1008_0020 |
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
42946 | Kintex-7 FPGA 设计咨询主答复记录 | N/A | N/A |
AR# 51884 | |
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日期 | 10/12/2012 |
状态 | Active |
Type | 设计咨询 |
器件 |