| (Xilinx Answer 66647) | UltraScale GTH and GTY transceivers bias voltage on MGTAVTT caused by negative current under some startup conditions |
| (Xilinx Answer 66160) | ADS - Example simulation project using IBIS-AMI models of UltraScale GTY |
| (Xilinx Answer 66341) | UltraScale GTY Transceiver: TX and RX Latency Values |
| (Xilinx Answer 66517) | Manual Eye Scan with UltraScale GTY in 10 steps |
| (Xilinx Answer 66341) | UltraScale GTY Transceiver: TX and RX latency values |
| (Xilinx Answer 65111) | UltraScale RX/TXUSRCLK routing |
| (Xilinx Answer 59834) | My UltraScale device package is showing 2 power groups for the MGT power supplies when there is only one column of GTs |
| (Xilinx Answer 64062) | UltraScale GTY RX reset in Near End PMA loopback (TX->RX serial loopback) |
| (Xilinx Answer 62527) | UltraScale GTY: how to set the CDR to "lock to local reference clock" |
| (Xilinx Answer 64103) | UltraScale GTH/GTY TX/RX PROG DIV block reset requirements |
| (Xilinx Answer 61723) | UltraScale GTH and GTY transceivers reference clock AC coupling capacitor value |
| (Xilinx Answer 63391) | My UltraScale GTY line rate violates the minimum value in Table 58 of the data sheet |
| (Xilinx Answer 63704) | UltraScale GTH/GTY - How to switch to use internal PRBS pattern generator when using Asynchronous Gearbox mode |
| (Xilinx Answer 64012) | Synchronous gearbox normal (non-CAUI) usage for 128-bit fabric interface (64-bit internal) UltraScale GTY |
| (Xilinx Answer 61946) | Virtex UltraScale GTY - UG578 v1.0 - incorrect description for reference clock selection above 16.375 Gbps |
| (Xilinx Answer 62261) | Datarate limitation for GTY TX Phase Interpolator usage |