2. 技术支持
  3. AR# 7070: NGDBuild/Virtex 2.1i: ERROR:NgdHelpers:312 - logical block "I_from_net_GND" of type "GND" is unexpanded
  4. AR# 70702: Zynq UltraScale+ MPSoC - PS/PL PCIe Drivers - Release Notes

AR# 70702

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Zynq UltraScale+ MPSoC (PS-PCIe/PL-PCIE XDMA Bridge) /Versal ACAP (CPM4/PL-PCIE4 QDMA Bridge) - Drivers Release Notes

描述

This answer record contains known Issues and information related to the drivers for:
  • PS PCIe and PL PCIe XDMA Bridge in Zynq UltraScale+ MPSoC
  • CPM4 and PL-PCIE4 QDMA Bridge in Versal ACAP devices.
For the list of available PCIe Embedded drivers, see: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/85983409/Xilinx+PCIe+Root+Port 

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

解决方案

Known Issues - [Zynq UltraScale+ MPSoC] PS-PCIe Driver

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 69066)Zynq UltraScale+ MPSoC Controller for PCI Express (Vivado 2017.1) - Root Port Error: hwirq 0x4 is too large for dummy2017.1

 

2018.1

 

(Xilinx Answer 76288)pci 0000:00:00.0: Failed to add - passthrough or MSI/MSI-X might fail!2020.2N/A, Workaround Provided


Known Issues - [Zynq UltraScale+ MPSoC] PL-PCIe XDMA Bridge Driver

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 70703)Zynq UltraScale+ MPSoC (Vivado 2017.4) - Issue fixes in driver for DMA/Bridge Subsystem for PCIe in AXI Bridge mode (PL PCIe) configured as Root Port2017.32018.1
(Xilinx Answer 69587)Zynq UltraScale+ MPSoC: Linux hangs when accessing PL peripheral by Yocto (2017.1 - 2017.4) - ILA / HW Manager usage with core in PetaLinux requires bootarg2017.1NA
(Xilinx Answer 71106)Zynq UltraScale+ MPSoC - PL PCIe Root Port Bridge (Vivado 2018.1) - MSI Interrupt handling causes downstream devices to time out2018.1NA
(Xilinx Answer 72389)Zynq UltraScale+ MPSoC (Vivado 2019.1) - PL-PCIe Root Port - Driver Compilation Fails2019.1NA, Patch Provided
(Xilinx Answer 72638)Zynq UltraScale+ MPSoC (Vivado 2019.1) - PL-PCIe Root Port - Multi-device MSI assignment broken2019.1NA, Patch Provided

Known Issues - [Versal ACAP] CPM4 Bridge Driver

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 76652)Enabling CPM4 Bridge Mode Root Complex Linux Driver2021.1

 

NA

 

(Xilinx Answer 76664)Running CPM4 Bridge Mode Root Port Baremetal Driver2021.1

NA


Known Issues - [Versal ACAP] PL-PCIE4 QDMA Bridge Driver

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 76665)PL-PCIE4 QDMA Bridge Mode Root Port Baremetal Driver Support2021.1

 

NA

 

(Xilinx Answer 76647)PL-PCIE4 QDMA Bridge Mode Root Port Linux Driver Support2021.1

NA



Other Information:

(Xilinx Answer 70854)Zynq UltraScale+ MPSoC - DMA/Bridge Subsystem for PCI Express - PL Bridge Root Port - IP Setup tips for use with PL PCIe Root Port driver
(Xilinx Answer 65443)DMA Subsystem for PCI Express - Release Notes and Known Issues for Vivado 2015.3 and newer tool versions

 

Related Answer Records on DMA/Bridge Subsystem for PCI Express:

(Xilinx Answer 70706)DMA/Bridge Subsystem for PCI Express (Bridge Mode/Root Port - Vivado 2017.4) - AXI transactions fail when no Endpoint is connected
(Xilinx Answer 71094)Zynq UltraScale+ MPSoC - DMA/Bridge Subsystem for PCIe (AXI Bridge mode/Root Port - Vivado 2018.1) - When 64-bit address is set in AXIBAR2PCIEBAR, endpoint PCIe BAR not enumerated in correct locations
(Xilinx Answer 71095)DMA / Bridge Subsystem for PCI Express (Bridge Mode - Vivado 2017.4) - AXIBAR and AXIBAR_HIGHADDR are set incorrectly in IPI design resulting in DECERR during 64-bit S_AXI access
(Xilinx Answer 71105)DMA Subsystem for PCI Express (Vivado 2018.1) - MSI Interrupt FIFO can overflow in Root Port configuration in Bridge Mode

Note: See (Xilinx Answer 65443) for other related information

 

Design Advisory:

(Xilinx Answer 70838)Design Advisory for AXI SmartConnect with PCI Express IP - Interoperability Issue - Data request upsize causes potential data corruption

Revision History:

06/03/2018 - Initial Release

 

链接问答记录

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
71094 Zynq UltraScale+ MPSoC - DMA/Bridge Subsystem for PCIe (AXI Bridge mode/Root Port - Vivado 2018.1) - When 64-bit address is set in AXIBAR2PCIEBAR, endpoint PCIe BAR not enumerated in correct locations N/A N/A
70854 Zynq UltraScale+ MPSoC - DMA/Bridge Subsystem for PCI Express - PL Bridge Root Port - IP Setup tips for use with the PL PCIe Root Port driver N/A N/A
70706 DMA/Bridge Subsystem for PCI Express (Bridge Mode/Root Port - Vivado 2017.4) - Bridge Mode - Root Port - AXI transactions fail when no Endpoint is connected N/A N/A
71106 Zynq Ultrascale+ MPSoC - PL PCIe Root Port Bridge (Vivado 2018.1) - MSI Interrupt handling causes downstream devices to time out N/A N/A
71095 DMA / Bridge Subsystem for PCI Express (Bridge Mode - Vivado 2017.4) - AXIBAR and AXIBAR_HIGHADDR are set incorrectly in IP Integrator design resulting in DECERR during 64-bit S_AXI access N/A N/A
70703 Zynq UltraScale+ MPSoC (Vivado 2017.4) - Issue fixes in driver for DMA/Bridge Subsystem for PCIe in AXI Bridge mode (PL PCIe) configured as Root Port N/A N/A
71105 DMA Subsystem for PCI Express (Vivado 2018.1) - MSI Interrupt FIFO can overflow in Root Port configuration in Bridge Mode N/A N/A
70838 支持 PCI Express IP 的 AXI Smartconnect 的设计咨询 — 互操作性问题：数据请求的增多会导致潜在的数据损坏问题 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
65443 DMA Subsystem for PCI Express - Release Notes and Known Issues for Vivado 2015.3 and newer tool versions N/A N/A
AR# 70702
日期 08/13/2021
状态 Active
Type 版本说明
IP
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