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Design Hubs
Vivado 2021.1 - High-Level Synthesis (C based)
Vivado 2021.1 - High-Level Synthesis (C based)
Choose version:
2020.1
2019.2
2019.1
Introduction
Date
Getting Started with Vivado High-Level Synthesis
01/07/2016
UG998 -
Introduction to FPGA Design Using High-Level Synthesis
01/22/2019
UG871 -
Vivado Design Suite Tutorial: High-Level Synthesis
08/07/2020
UG902 -
Vivado Design Suite User Guide: High-Level Synthesis
06/03/2020
UG1197 -
UltraFast High-Level Productivity Design Methodology Guide
06/03/2020
Key Concepts
Date
Packaging Vivado HLS IP for use from Vivado IP Catalog
09/17/2013
Verifying your Vivado HLS Design
09/17/2013
UG902 -
Properly Defining Interfaces in High-Level Synthesis
06/03/2020
UG902 -
Recommended Coding Styles
06/03/2020
UG902 -
Design Optimization
06/03/2020
UG1197 -
C-Based IP Development
06/03/2020
Frequently Asked Questions (FAQ)
Date
UG902 -
Where Do I Find Vivado HLS Examples?
06/03/2020
AR50502 -
Why Does the Report Show a "?" for the Latency Values?
10/05/2012
AR51081 -
Do I Need a License for Vivado HLS?
Xilinx Licensing FAQ
UG973 -
Vivado Design Suite Release Notes, Installation, and Licensing Guide
02/03/2021
UG902 -
How Do I Debug Cosimulation Failures?
06/03/2020
Additional Learning Materials
Additional Learning Materials
Methodology Guides
Design Files
Date
UG1270 -
Vivado HLS Optimization Methodology Guide
04/04/2018
Videos
Design Files
Date
Using the Vivado HLS Tcl Interface
12/14/2012
Floating Point Design with Vivado HLS
09/17/2013
Using Vivado HLS SW Libraries in your C, C++, System C Code
09/17/2013
Generating Vivado HLS block for use in System Generator for DSP
09/17/2013
Using Vivado HLS C/C++/System C block in System Generator
12/14/2012
Vivado HLS In-depth Technical Overview
09/23/2013
Application Notes
Design Files
Date
XAPP1341 -
PID Controller Design with Model Composer
Design Files
03/14/2019
XAPP1317 -
Scalable Floating-Point Matrix Inversion Design Using Vivado High-Level Synthesis
Design Files
10/02/2017
XAPP1300 -
Demystifying the Lucas-Kanade Optical Flow Algorithm with Vivado HLS
Design Files
02/03/2017
XAPP1299 -
Designing a Digital Up-Converter using Modular C++ Classes in Vivado High Level Synthesis Tool
Design Files
12/10/2016
XAPP1273 -
Reed-Solomon Erasure Codec Design Using Vivado High-Level Synthesis
Design Files
03/14/2016
XAPP1236 -
Multi-Channel Fractional Sample Rate Conversion Filter Design Using Vivado High-Level Synthesis
Design Files
12/15/2016
XAPP1209 -
Designing Protocol Processing Systems with Vivado HLS
Design Files
08/08/2014
XAPP599 -
Floating-Point Design with Vivado HLS
09/20/2012
XAPP1163 -
Floating-Point PID Controller Design with Vivado HLS and System Generator for DSP
Design Files
01/23/2013
XAPP1170 -
A Zynq Accelerator for Floating Point Matrix Multiplication Designed with Vivado HLS
Design Files
01/21/2016
XAPP1173 -
Implementing Carrier Phase Recovery Loop Using Vivado HLS
Design Files
05/02/2013
White Papers
Design Files
Date
WP491 -
Reduce Power and Cost by Converting from Floating Point to Fixed Point
03/30/2017
WP452 -
Adaptive Beamforming for Radar: Floating-Point QRD+WBS in an FPGA
06/24/2014
Training
Design Files
Date
C-based Design: High-Level Synthesis with the Vivado ML Tool
Support Resources
Support Resources
How To Questions
Date
UG902 -
How Do I Apply Optimizations to an HLS Design?
06/03/2020
UG902 -
How Do I Control the Hardware Reset Behavior?
06/03/2020
UG902 -
How Do I Use the Output with Zynq-7000 SoC and SDK?
06/03/2020
AR54897 -
How Do I Implement a Global Clock Enable in a Vivado HLS Design?
AR46243 -
How Do I Run an RTL Simulation Using a Third-Party RTL Simulator?
08/06/2012
AR46111 -
How Do I Use #define in Pragmas?
10/09/2013
Solution Center
Date
AR47428 -
Xilinx Vivado HLS Solution Center
07/17/2019
Forum
Date
Xilinx User Community Forums - Vivado High-Level Synthesis (HLS)
Vivado Design Suite Product Page
Design Hubs Home Page
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