AR# 54897

描述

解决方案

For the clock enable, from the GUI select: Solution > Solution Settings > General > Add > Command: config_interface > Check the clock_enable.
This adds a port ap_ce port in your interface which acts as a clock enable.

Keep in mind that the ap_ce signal is also used as a gate signal for all outputs, which can have undesired effects in a multi-rate system in a System Generator design.

For EDK designs, this port will not be mapped on the axi4 lite control bus, but as a separate port; if the global clock gating functionality was required, the ap_start signal can be used as it will also prevent the core from running.