2. 技术支持
  3. AR# 4624: M1.5i/2.1i: Timing Analyser cannot be used to analyse a path through the asych PRE/CLR of an XC9500 FDCP
  4. AR# 46243: Vivado HLS - How do you run RTL simulation with a standalone RTL simulator?

AR# 46243

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Vivado HLS - How do you run RTL simulation with a standalone RTL simulator?

描述

How do you run RTL simulation with a standalone simulator without invokingC co-simulation?

解决方案

Vivado HLS

With Vivado HLS, click on Co Simulation icon and check Verilog or VHDL for RTL selection. Optionally, select "Setup Only" to just generate the files. ClickOK to generate the files.

The scripts and wrappers will be generated and placed in the project's solution/sim/verilog (or vhdl) folder. To run simulation with Modelsim, source run_modelsim.sh file.

AutoESL

In the AutoESL tool, open the RTL Simulation dialog and check "Setup Only" to generate RTL wrapper and scripts. The AutoESL tool generates scripts for ModelSim.

When scripts and wrappers have been generated, perform the following steps to run simulation with ModelSim:

  1. change directory to <autoesl project>/solution1/sim/verilog
  2. source compile_modelsim.sh
  3. source autosim.modelsim.scr

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A
AR# 46243
日期 08/06/2012
状态 Active
Type 解决方案中心
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