11-27-2018 07:31 PM

When the progenitors of Ethernet at Xerox PARC created their first (3Mb/s) version in the late 1970s, they focused their efforts on connectivity, and paid little attention to network latency or throughput. Network nodes back then were humans at workstations and laser printers, and nobody cared if packets interfered with one another in transit, and had to be retransmitted many times before reaching their destinations. Mixing long and short packets on the network resulted in long delays for short packets, as they waited for longer packets to go by, in much the same way as autos at a railroad crossing wait for a train to pass before they can get to the other side.

Fast forward to today, when Ethernet speeds have accelerated significantly. The higher speeds greatly enhance capacity, but do little to manage latency or optimize bandwidth. It’s still OK to drop and retransmit packets in heavily loaded situations. Realizing that this would limit the utility of Ethernet in applications that require precise and deterministic timing, the IEEE 802 committee that oversees Ethernet specifications created a new set of sub-standards collectively referred to as “Time Sensitive Networking (TSN),” that allow various classes of network traffic to share a common link.

Getting TSN to work is an enormously challenging technical problem. In classic Ethernet, once a node starts sending packet “A”, it must complete that transmission before starting another. But what happens if another packet “B” that might miss a deadline if delayed suddenly comes to the head of the queue? The sender must wait for the first packet to complete, or abort that transmission, send packet “B”, and then resend packet “A” in its entirety later, thus trading off bandwidth to minimize latency. In TSN-enabled networks, the transmitting node can effectively pause packet “A” in mid-flight, transmit packet “B”, and then resume sending “A” where it left off. Even with relatively slow (100Mb/s) networks, the controller has less than 82 microseconds(µs) to evaluate queuing options and decide what to do--and the window narrows to 8 µs at gigabit speeds.

Implementing TSN requires a combination of the decision-making capabilities of microprocessors and the dedicated circuitry of FPGAs. Not surprisingly, Xilinx has been intimately involved with two groups --the AVnu Alliance and the Industrial Internet Consortium – that have been working on TSN for several years. At the 2016 SPS IPC Drives trade fair in Nuremberg, we demonstrated key industrial protocols including OPC UA, DDS, and EtherCAT running on top of TSN. In 2017 we released a preliminary version of our TSN support with the catchy title “1G/100M TSN Subsystem LogiCORE IP.” It works with our Zynq-7000 or Zynq UltraScale+ MPSoC devices, and provides single chip solutions for a range of applications. At this week’s SPS IPC Drives event in Nuremberg, we are demonstrating an Acutronic Robotics’ MARA Collaborative robot (Cobot) that is critically dependent on real-time motion control for speed, accuracy, and safety. Xilinx’s Zynq-based TSN solution manages the deterministic Ethernet-based communication capabilities used in multi-axis cobots.

Other early-access customers have also attained excellent technical results that they anticipate will benefit their bottom lines. General Electric noted: “In our internal testing, the Xilinx IP core has met some of our most stringent requirements. From a sheer performance perspective, we observed a packet delay variation of less than 50 nanoseconds peak-to-peak. We found the Xilinx IP core to have extensive coverage of TSN specifications. Due to the flexibility of an IP core, Xilinx has been able to upgrade it over time as standards mature and add new features, which fits nicely with our product development lifecycle.”

In all, since we announced this package, dozens of customers have obtained licenses to incorporate Xilinx TSN IP into their products. To help developers get started on their TSN projects, we’ve teamed up with Avnet to offer a TSN Evaluation Kit (AES-ZU-TSN-SK-G) at a special promotional price of $10,000 until December 31, 2018. (A time-sensitive offer for time-sensitive IP.) The kit includes two hardware TSN nodes developed by Avnet, comprising a total of six boards, and a full project license which entitles users to deploy Xilinx’s TSN Endpoint IP on Zynq or Zynq UltraScale+ SoCs in production. In 2019, the price for this kit will revert to its usual price of $27,000, so it pays to act now. Call your local Xilinx or Avnet sales contact for details.

Time-Sensitive Networking is one of many areas that benefit enormously from Xilinx’s adaptable and intelligent platforms. The computational tasks are demanding, but real-time constraints preclude simple microprocessor-based solutions. Rapidly evolving standards complicate custom ASIC solutions. These are the types of applications our architects and designers envisioned when they designed these products. We’re glad that our customers recognize the value of our approach, and together we can take on even more challenging problems yet to be solved.