The Xilinx DDR3 controller is high performance (2133Mbps in UItraScale) with support for lower power DDR3L as well as UDIMMs, SODIMMs, and RDIMMs.
Product Description
The Xilinx DDR3 core can generate a full controller or phy only for custom controller needs. The Controller will run up to 2133Mbps in UltraScale devices. The controller is configurable through the IP catalog. The controller will support data widths from 8b to 80b and multiple memory types including components, UDIMM, SODIMM, and RDIMMs. Comprehensive in system testing across PVT corners is done to ensure first time success. Additional debug capabilities are provided like the Advanced Traffic Generator which allows in system testing with PRBS or custom traffic patterns to isolate bit errors on the read or write side. A powerful simulation environment allows you to quickly calculate efficiency based on your traffic patterns. Simple tweaks to the controller settings can help tune and find the best efficiencies.
Key Features and Benefits
- Component support for interface width of 8 to 80 bits (RDIMM, UDIMM, and SODIMM support)
- Controler / Phy mode or Phy only mode, plus Ping Pong Phy option
- DDR3 (1.5V)
- DDR3L (1.35V)
- 8 GB component device support
- Dual slot support for UDIMMs, SODIMMs and RDIMMs
- Dual Rank support for DIMMs
- x4, x8, and x16 device support
- 8:1 DQ:DQS ratio support for x8 and x16 devices
- 4:1 DQ:DQS ratio support for x4 devices
- 8-word burst support
- Support for 5 to 14 cycles of column-address strobe (CAS) latency (CL)
- On-die termination (ODT) support
- Support for 5 to 10 cycles of CAS write latency
- Write leveling support for DDR3 (fly-by routing topology required component designs)
- JEDEC®-compliant DDR3 initialization support
- Source code delivery in Verilog
- 4:1 memory to FPGA logic interface clock ratio
- Open, closed, and transaction based pre-charge controller policy
- Interface calibration and training information available through the Vivado hardware manager