AR# 18329

描述

To be fully compliant, a PCI Express add-in card is required to use the 100 MHz reference clock from the PCI Express Connector. The add-in card must use the connector clock to clock the MGT blocks on the Xilinx device.

How do I clock the Xilinx FPGA when implementing PCI Express solutions?

解决方案

IMPORTANT: For Virtex-6, Virtex-5, Virtex-4, Virtex-II Pro, and Spartan-6 FPGA PCI Express add-in cards to work in an open system, they must be clocked off the central motherboard clock resource so that they are frequency-locked with the motherboard clock (i.e., synchronously clocked). Add-in cards clocked with their own on-board oscillator (i.e., asynchronously clocked) do not work in open systems.

Asynchronous Clocking

7 Series, Virtex-6 and Spartan-6 FPGAs

Asynchronous clocking can be used in embedded or backplane applications with Virtex-6 and Spartan-6 FPGAs when SSC and ASPM are not used. The designer must guarantee that neither the oscillator sourcing the Xilinx FPGA nor the oscillator sourcing the link partner device uses Spread Spectrum Clocking (SSC). Also, both clocks must meet the ppm tolerance requirements of the PCI Express specification and the Xilinx FPGA. Asynchronous clocking cannot be used when SSC is used.

Xilinx is currently investigating support of asynchronous clocking when ASPM is enabled. Currently asynchronous clocking is not supported when ASPM is in use. ASPM is hardware autonomous Active State Power Management in which an idle link reduces power by going into the L0s state where electrical idle is driven on the link without the intervention of software. See Chapter 5 of the PCI Express Base Specification for more information on ASPM. To know if ASPM is in use, the user can view bits 1:0 of the Link Control register found at offset 10h of the PCI Express Capability Set. ASPM cannot be disabled on the endpoint, but can sometimes be disabled on the downstream port through changes in the BIOS. Alternatively, a possible work around to force the system to disable ASPM is to set the L0s Exit latency to its maximum value (111b), and set the L0s Acceptable latency to a low value and the power management firmware may not enable ASPM. These settings are available through the customization GUI. The 7 Series Integrated Block supports ASPM Optionality meaning that in newer systems that support ASPM Optionality, ASPM can be turned off using this option.

The following diagrams are high-level representations of the board layout. You must ensure that proper coupling and termination are used when laying out your board.

Click on the device in use:

7 Series
Virtex-6
Spartan-6
Virtex-5
Virtex-4
Virtex-II Pro

7 Series Gen 1 and Gen 2

The7 series FPGA Integrated Block for PCI Express can be clocked with a 100, 125 or 250 MHz system reference clock for both GEN 1 and GEN 2 applications. Use the CORE Generator GUI to select the appropriate reference clock frequency. For 125 or 250 MHz, an external PLL must be used to convert the 100 MHz system clock to 125 or 250 MHz. Using 100 MHz reference clock is compliant; the option to use 125 MHz or 250 MHz allows users more flexibility and more TX jitter margin if needed.

100 MHz Reference Clock



125 or 250 MHz Reference Clock





Virtex-6 FPGA Gen 1 and Gen 2

The Virtex-6 FPGA Integrated Block for PCI Express can be clocked with a 100, 125 or 250 MHz system reference clock for both GEN 1 and GEN 2 applications. Use the CORE Generator GUI to select the appropriate reference clock frequency. For 125 or 250 MHz, Xilinx recommends using the ICS874001AG-05LF to accomplish the conversion from 100 MHz to 125 or 250 MHz. Using 100 MHz reference clock is compliant; the option to use 125 MHz or 250 MHz allows users more flexibility and more TX jitter margin if needed.

Data sheets on Integrated Circuit Systems, Inc., parts are available at:
http://www.idt.com

For more information, please contact IDT at:
netcom@idt.com

100 MHz Reference Clock





125 or 250 MHz Reference Clock




Spartan-6 FPGA

The Spartan-6 FPGA Integrated Block for PCI Express can be clocked with a 100 or 125 MHz system reference clock. Use the CORE Generator GUI to select the appropriate reference clock frequency. For 125, Xilinx recommends using the ICS874001AG-05LF to accomplish the conversion from 100 MHz to 125 MHz , as shown in Figure 5. Using 100 MHz reference clock is compliant; the option to use 125 MHz allows users more flexibility and more TX jitter margin if needed.

For the v1.2 release see (Xilinx Answer 33761) for information on how to enable the 100 MHz reference clock. The GUI will not include this feature until the v1.3 release in ISE software 12.1.

Data sheets on Integrated Circuit Systems, Inc., parts are available at:
http://www.idt.com

For more information, please contact IDT at:
netcom@idt.com

100 MHz Reference Clock





125 MHz Reference Clock




Virtex-5 FPGA
PCI Express GEN 2 (Virtex-5 FXT FPGA only)

PCIe GEN 2 requires a 250 MHz input reference clock. The 250 MHz reference clock must be derived from the 100 MHz reference clock from the PCI Express connector. It must be multiplied up to 250 MHz while at the same time remaining compliant to the jitter specifications required by the Virtex-5 FPGA MGT. Xilinx recommends using the ICS874003BG-05 to accomplish the conversion from 100 MHz or 250 MHz , as shown in Figure 5. This PLL meets the PCIe GEN2 PLL bandwidth requirements.

Data sheets on Integrated Circuit Systems, Inc., parts are available at:
http://www.idt.com

For more information, please contact IDT at:
netcom@idt.com

PCI Express Gen 1

The Xilinx Endpoint Block Plus Core for PCI Express can be clocked with either a 100 or 250 MHz system reference clock. Use the CORE Generator GUI to select the appropriate reference clock frequency. Using 100 MHz reference clock is compliant; the option to use 250 MHz allows users more flexibility and more TX jitter margin if needed. For v1.1 PCI Express compliance, the IDT PLLs mentioned below must meet the bandwidth requirements stated in section 4.3.3.3 of the PCI Base Specification v1.1. Newer revisions of the IDT parts (ICS874003CGI-02and 874003DGI-02) meet this requirement. For more information please contact IDT at: netcom@idt.com.

Using a 100 MHz Reference Clock

The 100 MHz clock provided by the PCI Express connector can be connected directly to the Virtex-5 FPGA to clock the PCI Express Endpoint Block and PCI Express Endpoint Block Plus LogiCORE, as shown in Figure 6.








250 MHz Reference Clock

The 250 MHz reference clock must be derived from the 100 MHz reference clock from the PCI Express connector. It must be multiplied up to 250 MHz while at the same time remaining compliant to the jitter specifications required by the Virtex-5 MGT. Xilinx recommends using the ICS874003-02 to accomplish the conversion from 100 MHz or 250 MHz, as shown in Figure 7. Data sheets on Integrated Circuit Systems, Inc., parts are available at: http://www.idt.com

For more information, please contact IDT at:
netcom@idt.com

Virtex-4

The Xilinx LogiCORE IP Endpoint for PCI Express when targeted to a Virtex-4 device requires a 250 MHz reference clock.

When targeting the Virtex-4 device, the PCI reference clock input must be 250 MHz.

Note: If a 125 MHz clock is used, the total transmit jitter generated by the MGT violates the minimum transmit eye width specification of 0.75 UI as specified by the parameter Ttx-eye (Minimum TX Eye Width) in the PCI Express Base Specification v1.1. Consequently, Virtex-4 PCI Express designs should use a 250 MHz reference clock.

To use the 100 MHz PCI Express reference clock off the connector, it must be multiplied up to 250 MHz while at the same time remaining compliant to the jitter specifications required by the Virtex-4 MGT. Xilinx recommends two solutions to achieve the 100 MHz to 250 MHz conversion. These solutions are available to provide you with more flexibility in gaining access to parts. Each solution achieves the same result of converting the clock to 250 MHz. The first solution uses the ICS874003-02 to accomplish the conversion from 100 MHz to 250 MHz. The second solution uses two parts to perform the conversion. In this case, the ICS87354I divides the clock down to 25 MHz and the ICS8432I-101 multiplies the 25 MHz clock up to 250 MHz. Data sheets on Integrated Circuit Systems, Inc., parts are available at: http://www.idt.com

For more information, please contact IDT at:
netcom@idt.com

Single-Chip Solution

You can use the ICS874003-02 part to convert the 100 MHz clock to 250 MHz, as shown in Figure 8.






Two-Chip Solution

Xilinx also recommends another solution using two ICS parts. This solution uses the ICS87354I to divide the 100 MHz clock down to 25 MHz and the ICS8432I-101 to multiply the 25 MHz clock up to 250 MHz. This conversion is shown in Figure 9.






Virtex-II Pro

The Xilinx LogiCORE Endpoint for PCI Express, when targeted to a Virtex-II Pro device, requires a 125 MHz reference clock.

To use the 100 MHz PCI Express reference clock off the connector, it must be multiplied up to 125 MHz while at the same time remaining compliant to the jitter specifications required by the Virtex-II Pro MGT. One way to accomplish this is to use a ICS9DB306 to convert the 100 MHz clock to 125 MHz, and then use an ICS85411 to convert output of the ICS9DB306 to LVDS. Data sheets on Integrated Circuit Systems, Inc., parts are available at: http://www.idt.com

For more information, please contact IDT at:
netcom@idt.com

The following diagram illustrates the use of these two parts to create the 125 MHz MGT reference clock for the Virtex-II Pro RocketIOs.






The configuration above transforms the 100 MHz differential connector clock to a 125 MHz LVDS clock that meets the jitter requirements for the Virtex-II Pro RocketIO MGTs. You must ensure that the jitter and other specifications required by the Virtex-II Pro device (as shown in the device data sheet) are met during board layout.

For more information on clocking PCI Express systems, see (Xilinx Answer 19760).
For more information on SSC in PCI Express systems, see (Xilinx Answer 19782).

Revision History
02/03/2012 - Updated Asynchronous clocking information for 7 series FPGAs.
03/14/2011 - Added 7 Series Information
11/01/2010 - Fixed problem with repeating figures.
08/27/2010 - Added information about asynchronous clocking and ASPM
02/22/2010 - Fixed line spacing problems and image ordering.
01/29/2010 - Added 100 MHz for Virtex-6 Gen 2
11/18/2009 - Fixed heading for Spartan-6 FPGA 125 MHz conversion to remove mention of 250 MHz.
11/09/2009 - Removed 250 MHz option for Spartan-6 FPGA. See (Xilinx Answer 33774) Fixed link to AR 33761.
11/05/2009 - Added 100 MHz clocking for Spartan-6 FPGA
10/15/2009 - Removed restriction on Virtex-6 FPGA Non-synch clocking; Fixed typo in Virtex-5 Gen 1 section to not specifically refer to LXT
09/22/2009 - Updated for Virtex-6 and Spartan-6 FPGA
02/02/2009 - Added note on non-synchronous clocking.
10/30/2008 - Added PCIe GEN 2 requirement.
08/27/2008 - Updated to remove 125 MHz from Virtex-5 FPGA discussion since Block Plus core only accepts 100 or 250 MHz.

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