AR# 32757

描述

This Answer Record contains the Release Notes for the LogiCORE CPRI v2.2 Core, released in the ISE 11.2, and includes the following: 

- New Features 

- Bug Fixes  

- Known Issues 

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: 

http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

解决方案

New Features  

- ISE 11.2 support added 

- Virtex-6 support added 

Resolved Issues  

(Xilinx Answer 32517) LogiCORE CPRI v2.1 - When using Virtex-5 FXT, the second GTX value for attribute PMA_CDR_SCAN is not optimal  

(Xilinx Answer 32645) LogiCORE CPRI v2.1 - Virtex-5 FXT - Missing constraint in Example Design UCF 

- IR 519309: Master core CDC FIFO does not infer block RAM in Virtex-6. 

- IR 490086: Possibility of first RX Strobe arriving earlier than expected. 

- IR 473738: Slave toggles TX inhibit at startup. 

Known Issues 

- Virtex-6 solutions are pending hardware validation. 

-Software Support for the Virtex-6 Lower Power parts was added in this release, but the CPRI core does not yet support these devices and cannot be generated from CORE Generator targeting Virtex-6 Lower Power. Pending further testing support for Virtex-6 Lower Power parts is planned for 11.3. In order to work around this issue, you can set your project to target an equivalent Virtex-6 LXT device which will allow you to generate the IP.

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